From patchwork Thu Jan 9 11:38:14 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Vladimir Kondratiev X-Patchwork-Id: 13932430 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8F8FCE77197 for ; Thu, 9 Jan 2025 11:38:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=McJKrUvstpRu/G/ewGkaH8M7XV+biZZmhZqLfyyOPnU=; b=OgTpXClCeQMc7m eaHRj21JnY2JokwPsLdRR9wRj845i4gyaLzDMHYPj1vaVYutPP6ziN9M9nKk8o9tu7WlYxtrmnwek PibECxMOsF6PHkPVg5V0j+A167V/2Qz9rvKCN3xyUEpNy58djB9Md08esQC+975yS0fsu0Hfo/xo1 u6qx1xfomacXMBkWtLUn7NwtO+gIM0M3Zm/O/eQ0p/DTjWEPLmevplbY+8xSjmONKhgvAT2HKK2ZO DO4HuezN9dvgHyIskxHoKK2cX6n5aAfiQwA0sN1J+g2xhf0dWqlhJw57QAhOpNpmuMdeYkElCq3X+ DKblLSxPQm1198Ov0laQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tVqs9-0000000BkN9-2q2R; Thu, 09 Jan 2025 11:38:45 +0000 Received: from esa4.hc555-34.eu.iphmx.com ([207.54.77.171]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tVqs4-0000000BkLU-3V46 for linux-riscv@lists.infradead.org; Thu, 09 Jan 2025 11:38:43 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=mobileye.com; i=@mobileye.com; q=dns/txt; s=MoEyIP; t=1736422720; x=1767958720; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=t4I+3GYTBD9R29FxQzIKQ/m13Ut3AEhZho/gtBtVzk8=; b=QqaNPO3F1/SPgg8oDhYFELXyd0eiq2dfjNL9NP3WRRCw8nhRsvW/bODq zTF5i1qj0UBLkBJArV8Ibtd4Eu4cnlyzdorq/TTVaNDvC1CHmPaM/tTQP XRDS/UQBAD7CgebhEhHkGP8FM2zinVdp4EaEIwfQ5he0flzZI/FfcUhE3 Mp5LTEEj7KjPVmSBTvFdUJ8OW1viWPYNPTbBCoXsT32S+a4A5WY+wrlnD KL54Mmj2YV4r4THFtg9pNSytLO1YgvyQXrlI1n6z+iZeEY2olclhZxpfH IE7Lv8cY2dwoHAfs2EY+BZdoz+wlhT2AhJ9c6a+8foRFGrsb0XvsiWET0 Q==; X-CSE-ConnectionGUID: tuwhMObWSYWBmS77usFRsw== X-CSE-MsgGUID: JTtJKNaYSdCBsdJPiKQP0Q== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from unknown (HELO ces01_data.me-corp.lan) ([146.255.191.134]) by esa4.hc555-34.eu.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jan 2025 13:38:37 +0200 X-CSE-ConnectionGUID: rRCfangzSQCGyCwuLbNjPA== X-CSE-MsgGUID: puy+xhY0TIOwl9XhfKbrdQ== Received: from unknown (HELO epgd022.me-corp.lan) ([10.154.54.1]) by ces01_data.me-corp.lan with SMTP; 09 Jan 2025 13:38:35 +0200 Received: by epgd022.me-corp.lan (sSMTP sendmail emulation); Thu, 09 Jan 2025 13:38:35 +0200 From: Vladimir Kondratiev To: Anup Patel , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Vladimir Kondratiev Subject: [PATCH v4 2/2] irqchip/riscv-aplic: add support for hart indexes Date: Thu, 9 Jan 2025 13:38:14 +0200 Message-ID: <20250109113814.3254448-3-vladimir.kondratiev@mobileye.com> In-Reply-To: <20250109113814.3254448-1-vladimir.kondratiev@mobileye.com> References: <20250109113814.3254448-1-vladimir.kondratiev@mobileye.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250109_033841_158002_9BB0A31C X-CRM114-Status: GOOD ( 19.76 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Risc-V APLIC specification defines "hart index" in [1]: Within a given interrupt domain, each of the domain’s harts has a unique index number in the range 0 to 2^14 − 1 (= 16,383). The index number a domain associates with a hart may or may not have any relationship to the unique hart identifier (“hart ID”) that the RISC-V Privileged Architecture assigns to the hart. Two different interrupt domains may employ entirely different index numbers for the same set of harts. Further, this document says in "4.5 Memory-mapped control region for an interrupt domain": The array of IDC structures may include some for potential hart index numbers that are not actual hart index numbers in the domain. For example, the first IDC structure is always for hart index 0, but 0 is not necessarily a valid index number for any hart in the domain. Support arbitrary hart indexes specified in optional APLIC property "riscv,hart-indexes" that should be array of u32 elements, one per interrupt target. If this property not specified, fallback is to use logical hart indexes within the domain. [1]: https://github.com/riscv/riscv-aia Signed-off-by: Vladimir Kondratiev Reviewed-by: Anup Patel --- drivers/irqchip/irq-riscv-aplic-direct.c | 25 +++++++++++++++++++++--- 1 file changed, 22 insertions(+), 3 deletions(-) diff --git a/drivers/irqchip/irq-riscv-aplic-direct.c b/drivers/irqchip/irq-riscv-aplic-direct.c index 7cd6b646774b..ea61329decb2 100644 --- a/drivers/irqchip/irq-riscv-aplic-direct.c +++ b/drivers/irqchip/irq-riscv-aplic-direct.c @@ -31,7 +31,7 @@ struct aplic_direct { }; struct aplic_idc { - unsigned int hart_index; + u32 hart_index; void __iomem *regs; struct aplic_direct *direct; }; @@ -219,6 +219,21 @@ static int aplic_direct_parse_parent_hwirq(struct device *dev, u32 index, return 0; } +static int aplic_direct_get_hart_index(struct device *dev, u32 logical_index, + u32 *hart_index) +{ + static const char *prop_hart_index = "riscv,hart-indexes"; + struct device_node *np = to_of_node(dev->fwnode); + + if (!np || !of_property_present(np, prop_hart_index)) { + *hart_index = logical_index; + return 0; + } + + return of_property_read_u32_index(np, prop_hart_index, + logical_index, hart_index); +} + int aplic_direct_setup(struct device *dev, void __iomem *regs) { int i, j, rc, cpu, current_cpu, setup_count = 0; @@ -265,8 +280,12 @@ int aplic_direct_setup(struct device *dev, void __iomem *regs) cpumask_set_cpu(cpu, &direct->lmask); idc = per_cpu_ptr(&aplic_idcs, cpu); - idc->hart_index = i; - idc->regs = priv->regs + APLIC_IDC_BASE + i * APLIC_IDC_SIZE; + rc = aplic_direct_get_hart_index(dev, i, &idc->hart_index); + if (rc) { + dev_warn(dev, "hart index not found for IDC%d\n", i); + continue; + } + idc->regs = priv->regs + APLIC_IDC_BASE + idc->hart_index * APLIC_IDC_SIZE; idc->direct = direct; aplic_idc_set_delivery(idc, true);