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Mon, 13 Jan 2025 07:09:54 -0800 (PST) From: Xu Lu To: daniel.lezcano@linaro.org, tglx@linutronix.de, anup@brainfault.org, paul.walmsley@sifive.com, palmer@dabbelt.com Cc: lihangjing@bytedance.com, xieyongji@bytedance.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Xu Lu Subject: [PATCH 3/5] irqchip/riscv-imsic: Use wmb() to order normal writes and IPI writes Date: Mon, 13 Jan 2025 23:09:31 +0800 Message-Id: <20250113150933.65121-4-luxu.kernel@bytedance.com> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20250113150933.65121-1-luxu.kernel@bytedance.com> References: <20250113150933.65121-1-luxu.kernel@bytedance.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250113_070955_854185_AF25BB29 X-CRM114-Status: UNSURE ( 8.15 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org During an IPI procedure, we need to ensure all previous write operations are visible to other CPUs before sending a real IPI. We use wmb() barrier to ensure this as IMSIC issues IPI via mmio writes. Signed-off-by: Xu Lu --- drivers/irqchip/irq-riscv-imsic-early.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/irqchip/irq-riscv-imsic-early.c b/drivers/irqchip/irq-riscv-imsic-early.c index 63097f2bbadf..c6317cb557fb 100644 --- a/drivers/irqchip/irq-riscv-imsic-early.c +++ b/drivers/irqchip/irq-riscv-imsic-early.c @@ -29,6 +29,12 @@ static void imsic_ipi_send(unsigned int cpu) { struct imsic_local_config *local = per_cpu_ptr(imsic->global.local, cpu); + /* + * Ensure that stores to normal memory are visible to the other CPUs + * before issuing IPI. + */ + wmb(); + writel_relaxed(IMSIC_IPI_ID, local->msi_va); }