From patchwork Wed Feb 5 15:59:47 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 13961500 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3118AC02198 for ; Wed, 5 Feb 2025 16:17:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=l67vx6+O+Gzz9kxEY1fAybGouRr4OJWWYxHIz/fmS4Q=; b=FsXabqEgE0u1Pg R7lic0v8t7hF0sDjkku20WnbrtS5L7Cn3kqCA4k3o5uVQ5AVqeG8el86wovbXrP3JgkJnbqPOJx6V XNWldaKCz60UUZ8upia9/3BW3BBRw0e5VwiFpS6giQMlSyhQrgIn05blNRIhvrqvg3oSA2bGDeKyz qV0NVjq9g+gvKmAZTS83HAyHmKeirJg4LPnUg4caBl/wDcHo/gqwskwtI6RrRjs0hl0DR0DuzOB65 N4JWG4FVJbqgawWdoSDWjDOPrN+8C32og4ZZQ27PKM/kXUkFGkESztH52oTFtB+VOFVbYTBFxFRgO Rb/RuU4TyZUtlOWH4I5g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tfi60-00000003wUe-1UfI; Wed, 05 Feb 2025 16:17:48 +0000 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tfhq1-00000003t9c-3iQR for linux-riscv@lists.infradead.org; Wed, 05 Feb 2025 16:01:19 +0000 Received: by mail-pl1-x629.google.com with SMTP id d9443c01a7336-21670dce0a7so9323805ad.1 for ; Wed, 05 Feb 2025 08:01:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1738771277; x=1739376077; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KEjndyBD35lV6nr6NSLWRRyly4db2axy7koFOHZTKsQ=; b=H5BQ6EI99cXdEEb5C2XpukoPYtVv6fMXEktKC92eLO0CPcUqEj8FD/qB5b2I7YG4jA t0wrc1577LM0vUrClIr3nUd5jlTdld/LtbpcSM2VOv7QVvVrG5uz+76dmhJOznoaH/ST Q1ClcjVyLMizB3uix2L/Pjv5aeAX1u9MdGax6BYar8wqsqBbxDw8xZxghLw5d/plrLNX EmMmwgc1RXpkRjsVXkvFSPhF+YuOVjlBmRNmHn8FhyhHZ2+9OC66aJQ+9xpghIawidxI sGjzKij/K/UaNX4LRq3oGfkYsU38JyRCm9LnJ+AAlfDVjf/Xge2AhLQqszRWMMiWiUWh kFLQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738771277; x=1739376077; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KEjndyBD35lV6nr6NSLWRRyly4db2axy7koFOHZTKsQ=; b=KyFgfEBW+GITWcqnUYsrm+TJIP876JN+Z14rj4oUQ8SQJwRJ3ELD54lpwA6rjF9ihc iL/hnlTc7DfFUGsUtNGj38c3oMWo4vdjnwbWTCCoQjh2G0clOBMdsy9Xhd38297pZpna DHtnUZYg9BaCtnzArdpjfu4yGcBZDSOZcoK5EPs/0yjSuJowEGWdBRtCR8Qnq9yaaUPr On+jYmzQBs7MyQ2w1g0paRH4DNT56Sfqkdeb8UJOIVv6Ck0uF05BgNhgmfcMvMjHN8k5 9SF0o14ds2b3n6Yh5KPDX6kTW325UTKJ3KICzSSnSv9Ygoc1KqS7UjWz4yyH0peOsFao ly2Q== X-Forwarded-Encrypted: i=1; AJvYcCXVzMhX6JdaDorGPw+In/hwQmvtS1YQetqhpCrhGImQdwf51IzoE7QINrXwHPwPYsbZ6b7xtXG+ajBsKg==@lists.infradead.org X-Gm-Message-State: AOJu0Yxn2HzhezYXP17wPm0jPcDmrJ7R8vYFAiUqxr85+Jv7NSE2bNMj D22i28YPxasY13L45ItGzk1l5M6rbIDOjuqqidjXk+tyHfDNzfR8ktnO9fgXbXI= X-Gm-Gg: ASbGnctqm+DnSVbC5mHXpOOFMm7rMRQGzeBqR7dtqET9M5m3M3EyrPjTJwrxmaQ3PrP 9ZIamnDvs4E2xnKidDPqbF24nmtoU56nkB0zsumqOxFfKRhRMmoa3R/a92t1WXzJxEq/ZqW+uEk VgYfwxOLxb2C2J7mU3qIlU9r61Lz2nkca1YS4ZTVUzKYehAPskpWWDUKpRjt0Fvae+I3dQzpKkm lap3nzwARDFXwSHYNf54GzucUSeDQMDUnoVrFfJMkAWhqzdqOe/REmNufICoavRAzz3RJqswOuq ma+ZrX3CCVmPiEsjbclwAHO1xJwbtSe+sixoejzVoMIJHFsaD1qkAuE= X-Google-Smtp-Source: AGHT+IFTclDON/r36LodehwMg78zlP6BqfcqB9QXn3ksA4PSt60KgNQ9lMw/GuAJ5JZoMSZ1KuB8Cw== X-Received: by 2002:a17:903:18f:b0:21f:75c:f7d3 with SMTP id d9443c01a7336-21f17ec7bd9mr56546085ad.38.1738771275532; Wed, 05 Feb 2025 08:01:15 -0800 (PST) Received: from anup-ubuntu-vm.localdomain ([103.97.166.196]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-21edddf883fsm99369015ad.4.2025.02.05.08.01.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Feb 2025 08:01:14 -0800 (PST) From: Anup Patel To: Thomas Gleixner Subject: [PATCH v4 11/11] irqchip/riscv-imsic: Special handling for non-atomic device MSI update Date: Wed, 5 Feb 2025 21:29:47 +0530 Message-ID: <20250205155948.81385-12-apatel@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250205155948.81385-1-apatel@ventanamicro.com> References: <20250205155948.81385-1-apatel@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250205_080117_920553_BF3652C7 X-CRM114-Status: GOOD ( 21.68 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Anup Patel , Andrew Lunn , imx@lists.linux.dev, Marc Zyngier , Sascha Hauer , Atish Patra , linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Palmer Dabbelt , Pengutronix Kernel Team , Paul Walmsley , Anup Patel , Andrew Jones , Shawn Guo , Gregory Clement , linux-arm-kernel@lists.infradead.org, Sebastian Hesselbarth Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Device having non-atomic MSI update might see an intermediate state when changing target IMSIC vector from one CPU to another. To avoid losing interrupt to such intermediate state, do the following (just like x86 APIC): 1) First write a temporary IMSIC vector to the device which has MSI address same as the old IMSIC vector but with MSI data matches the new IMSIC vector. 2) Next write the new IMSIC vector to the device. Based on the above, the __imsic_local_sync() must check pending status of both old MSI data and new MSI data on the old CPU. In addition, the movement of IMSIC vector for non-atomic device MSI update must be done in interrupt context using IRQCHIP_MOVE_DEFERRED. Signed-off-by: Anup Patel --- drivers/irqchip/irq-riscv-imsic-platform.c | 73 +++++++++++++++++++++- drivers/irqchip/irq-riscv-imsic-state.c | 31 +++++++-- 2 files changed, 98 insertions(+), 6 deletions(-) diff --git a/drivers/irqchip/irq-riscv-imsic-platform.c b/drivers/irqchip/irq-riscv-imsic-platform.c index 6bf5d63f614e..828102c46f51 100644 --- a/drivers/irqchip/irq-riscv-imsic-platform.c +++ b/drivers/irqchip/irq-riscv-imsic-platform.c @@ -64,6 +64,11 @@ static int imsic_irq_retrigger(struct irq_data *d) return 0; } +static void imsic_irq_ack(struct irq_data *d) +{ + irq_move_irq(d); +} + static void imsic_irq_compose_vector_msg(struct imsic_vector *vec, struct msi_msg *msg) { phys_addr_t msi_addr; @@ -97,6 +102,21 @@ static int imsic_irq_set_affinity(struct irq_data *d, const struct cpumask *mask bool force) { struct imsic_vector *old_vec, *new_vec; + struct imsic_vector tmp_vec; + + /* + * Requirements for the downstream irqdomains (or devices): + * + * 1) Downstream irqdomains (or devices) with atomic MSI update can + * happily do imsic_irq_set_affinity() in the process-context on + * any CPU so the irqchip of such irqdomains must not set the + * IRQCHIP_MOVE_DEFERRED flag. + * + * 2) Downstream irqdomains (or devices) with non-atomic MSI update + * must do imsic_irq_set_affinity() in the interrupt-context upon + * next interrupt so the irqchip of such irqdomains must set the + * IRQCHIP_MOVE_DEFERRED flag. + */ old_vec = irq_data_get_irq_chip_data(d); if (WARN_ON(!old_vec)) @@ -115,6 +135,33 @@ static int imsic_irq_set_affinity(struct irq_data *d, const struct cpumask *mask if (!new_vec) return -ENOSPC; + /* + * Device having non-atomic MSI update might see an intermediate + * state when changing target IMSIC vector from one CPU to another. + * + * To avoid losing interrupt to such intermediate state, do the + * following (just like x86 APIC): + * + * 1) First write a temporary IMSIC vector to the device which + * has MSI address same as the old IMSIC vector but MSI data + * matches the new IMSIC vector. + * + * 2) Next write the new IMSIC vector to the device. + * + * Based on the above, the __imsic_local_sync() must check pending + * status of both old MSI data and new MSI data on the old CPU. + */ + + if (!irq_can_move_in_process_context(d) && + new_vec->local_id != old_vec->local_id) { + /* Setup temporary vector */ + tmp_vec.cpu = old_vec->cpu; + tmp_vec.local_id = new_vec->local_id; + + /* Point device to the temporary vector */ + imsic_msi_update_msg(irq_get_irq_data(d->irq), &tmp_vec); + } + /* Point device to the new vector */ imsic_msi_update_msg(irq_get_irq_data(d->irq), new_vec); @@ -171,6 +218,7 @@ static struct irq_chip imsic_irq_base_chip = { .irq_force_complete_move = imsic_irq_force_complete_move, #endif .irq_retrigger = imsic_irq_retrigger, + .irq_ack = imsic_irq_ack, .irq_compose_msi_msg = imsic_irq_compose_msg, .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND, @@ -190,7 +238,7 @@ static int imsic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, return -ENOSPC; irq_domain_set_info(domain, virq, virq, &imsic_irq_base_chip, vec, - handle_simple_irq, NULL, NULL); + handle_edge_irq, NULL, NULL); irq_set_noprobe(virq); irq_set_affinity(virq, cpu_online_mask); irq_data_update_effective_affinity(irq_get_irq_data(virq), cpumask_of(vec->cpu)); @@ -229,15 +277,36 @@ static const struct irq_domain_ops imsic_base_domain_ops = { #endif }; +static bool imsic_init_dev_msi_info(struct device *dev, + struct irq_domain *domain, + struct irq_domain *real_parent, + struct msi_domain_info *info) +{ + if (!msi_lib_init_dev_msi_info(dev, domain, real_parent, info)) + return false; + + switch (info->bus_token) { + case DOMAIN_BUS_PCI_DEVICE_MSI: + case DOMAIN_BUS_PCI_DEVICE_MSIX: + info->chip->flags |= IRQCHIP_MOVE_DEFERRED; + break; + default: + break; + } + + return true; +} + static const struct msi_parent_ops imsic_msi_parent_ops = { .supported_flags = MSI_GENERIC_FLAGS_MASK | MSI_FLAG_PCI_MSIX, .required_flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | MSI_FLAG_PCI_MSI_MASK_PARENT, + .chip_flags = MSI_CHIP_FLAG_SET_ACK, .bus_select_token = DOMAIN_BUS_NEXUS, .bus_select_mask = MATCH_PCI_MSI | MATCH_PLATFORM_MSI, - .init_dev_msi_info = msi_lib_init_dev_msi_info, + .init_dev_msi_info = imsic_init_dev_msi_info, }; int imsic_irqdomain_init(void) diff --git a/drivers/irqchip/irq-riscv-imsic-state.c b/drivers/irqchip/irq-riscv-imsic-state.c index d0148e48ab05..3a2a381e4fa1 100644 --- a/drivers/irqchip/irq-riscv-imsic-state.c +++ b/drivers/irqchip/irq-riscv-imsic-state.c @@ -126,8 +126,8 @@ void __imsic_eix_update(unsigned long base_id, unsigned long num_id, bool pend, static bool __imsic_local_sync(struct imsic_local_priv *lpriv) { - struct imsic_local_config *mlocal; - struct imsic_vector *vec, *mvec; + struct imsic_local_config *tlocal, *mlocal; + struct imsic_vector *vec, *tvec, *mvec; bool ret = true; int i; @@ -169,13 +169,36 @@ static bool __imsic_local_sync(struct imsic_local_priv *lpriv) */ mvec = READ_ONCE(vec->move_next); if (mvec) { - if (__imsic_id_read_clear_pending(i)) { + /* + * Device having non-atomic MSI update might see an + * intermediate state so check both old ID and new ID + * for pending interrupts. + * + * For details, refer imsic_irq_set_affinity(). + */ + + tvec = vec->local_id == mvec->local_id ? + NULL : &lpriv->vectors[mvec->local_id]; + if (tvec && + !irq_can_move_in_process_context(irq_get_irq_data(vec->irq)) && + __imsic_id_read_clear_pending(tvec->local_id)) { + /* Retrigger temporary vector if it was already in-use */ + if (READ_ONCE(tvec->enable)) { + tlocal = per_cpu_ptr(imsic->global.local, tvec->cpu); + writel_relaxed(tvec->local_id, tlocal->msi_va); + } + + mlocal = per_cpu_ptr(imsic->global.local, mvec->cpu); + writel_relaxed(mvec->local_id, mlocal->msi_va); + } + + if (__imsic_id_read_clear_pending(vec->local_id)) { mlocal = per_cpu_ptr(imsic->global.local, mvec->cpu); writel_relaxed(mvec->local_id, mlocal->msi_va); } WRITE_ONCE(vec->move_next, NULL); - imsic_vector_free(&lpriv->vectors[i]); + imsic_vector_free(vec); } skip: