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Thu, 06 Feb 2025 05:20:25 -0800 (PST) Received: from L4CR4519N7.bytedance.net ([203.208.189.11]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-21f3683d987sm12170775ad.120.2025.02.06.05.20.20 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Feb 2025 05:20:25 -0800 (PST) From: Rui Qi X-Google-Original-From: Rui Qi To: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, ardb@kernel.org, haibo1.xu@intel.com, guohanjun@huawei.com, sunilvl@ventanamicro.com, samuel.holland@sifive.com, parri.andrea@gmail.com, ericchancf@google.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-efi@vger.kernel.org, Rui Qi Subject: [RFC 5/5] RISC-V: define ioremap_cache Date: Thu, 6 Feb 2025 21:19:26 +0800 Message-Id: <20250206131926.91289-6-qirui.001@bytedance.com> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <20250206131926.91289-1-qirui.001@bytedance.com> References: <20250206131926.91289-1-qirui.001@bytedance.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250206_052026_291553_5D0FF9F9 X-CRM114-Status: UNSURE ( 6.36 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Rui Qi Define ioremap_cache for riscv, otherwise it will cause compile errors for bert.c and einj.c Signed-off-by: Rui Qi --- arch/riscv/include/asm/io.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h index 1c5c641075d2..c81d2de007bc 100644 --- a/arch/riscv/include/asm/io.h +++ b/arch/riscv/include/asm/io.h @@ -134,6 +134,11 @@ __io_writes_outs(outs, u64, q, __io_pbr(), __io_paw()) #endif #include +#define ioremap_cache ioremap_cache +static inline void __iomem *ioremap_cache(phys_addr_t addr, size_t size) +{ + return (__force void *)ioremap_prot(addr, size, _PAGE_KERNEL); +} #ifdef CONFIG_MMU #define arch_memremap_wb(addr, size) \