From patchwork Tue Mar 4 12:00:16 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jones X-Patchwork-Id: 14000618 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 43581C282D3 for ; Tue, 4 Mar 2025 12:10:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=C0+VCgio1tUjlLnBhjdP1KU//uFP0aIvLX5Mxj6nLmk=; b=KBwJbPQl1j56xu jrZlQoNyHoBBsyxVLqskeCAYdUmO8o+KhK2FYqZWEX+iOz2ttrou68bc92ETluueFPvw917NTWHcU nhL7W+oo+M/QQ1qa6TFK61ktuChu0qZBg47dHv+65IOn+0qw0yfFXRD7gUR0yRD8MSenHLHA4YYiS bVVtdp6Rc75jh0/eSlo+wuQx89RnE7PnIn3A/tGEq0nlEe8wT6ZuIVD9gRf2epaYS4QjE7wkb18Pc QXPlQfnitPFgqqXymp/eAdTETvabqlNhnoMeNLSUEzFjjm8t9k+8ohKDTONjrRQttcqm5ifAKr/GR j6v/tNDOOZ+kZIX/KJqA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tpR6f-00000004ZbJ-3EHk; Tue, 04 Mar 2025 12:10:41 +0000 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tpQwc-00000004V6I-2fa5 for linux-riscv@lists.infradead.org; Tue, 04 Mar 2025 12:00:19 +0000 Received: by mail-wr1-x42a.google.com with SMTP id ffacd0b85a97d-390dd35c78dso3565634f8f.1 for ; Tue, 04 Mar 2025 04:00:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1741089617; x=1741694417; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dsOXXT+GJOZQxfHaJbyOnCfiUI8BUwrK26GnKW4Oj7U=; b=oL8pxaaUCRitafsnnNsvDLJvjnRvI9fXlAims+FMhe4T6JlX0FeYfuRFy1K7COLTQd iGSL3k/P6E+QLB4T1sbmyLJtszq7HrpB3rNt87Bxu3pmsIgLscPbh98Jk/fuw1ZXQty7 rI9Wv+WLPuMmFfcmPvtQG3NwZ/6xg7zhPR/VdNiLflMwluUNGzGgX35g1TOfqJbvo8iE 4mZrHhevWqsrPLWzptp9q71lQACTq281YxS43SReVZphRq96aAFCIsRAs0cB9mORK7w5 Go6/2wk/Z0uFDaNqBS4JS99YjzQR6VohYKH1YRHVPEb7S0d7raGOzwkLPpxGMC8ZcCBZ 0QAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741089617; x=1741694417; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dsOXXT+GJOZQxfHaJbyOnCfiUI8BUwrK26GnKW4Oj7U=; b=JGrMe8oDFy1w1CzDDz95c8u+IcyhSnKHaVo+ZlBUakkaOsY1C8CCVMzJ9Gz5T64DeW 26XASx43Q/gHBaNJbOZx0IELRc97SoquocTGFKZiSgSLEkhP6URk1KFuXVhsV7zkPno9 jllT8eO/hbgfTEvZ1mICAeNCywNrbefR+tpOq/sUz6p7RMtRHNy9of91aWL2UvfLVo4O uVWmAfFEfQU+9HRP5Dj8K7zKKx5hGrGdKSzSdjVs1JfiGKUhtNE9TjXFriqNmbJ7UgiS FhNt3oyc8euUqFR8KtxFXLMaTTvDNiodjYH+AAGIwL3b3ASUAkLWNE2TnaNf0M89uQ5z uneg== X-Gm-Message-State: AOJu0Yz2065hzUxhCY7cfs6+WqiD580mT1WTC6l2LyfOSrUtOF62C7H+ YySG1yqAmKSR5E5eF7XntqgS6EnEVUiZseIchYq/u7HHpbpuTikMAj8veKcaSoyfHDjSV17jgO8 k X-Gm-Gg: ASbGnctgxcUnYYHO3HZlkrSoBmb3fgWlBlFMteyT9azM2lhCF5vmr3BrPVwZPO6c19s 9E1MHgsmSYsTI0crZ/CQeKKKp+U+3ARDf3rgMJ/ezjEnFCJZ4dZsxtJsDdY/ytADU/Rvn3gAMu4 xF4aR28tZTtaQ3/iHLHG51bAw9z2JCueJxuqv1UKP6M1WQYat4xSa2Hl+Vme6IY9AG/qKGT5/9/ Xp0kDVP6+tN9p3gX+NkUgicB4o+kfnbWFWZIj8H0FtxoijrMW39eAEww38d6pSDkHDS3tVXpN3/ G1fwTw5nOI1e7a3BPJ90foO3Wxu/6H7h X-Google-Smtp-Source: AGHT+IHfvp/euog7c3Gu4POXjA8Lq4HBzrln9LMIjOKJFZe5dI3SCeWKlW6YsuSzufoq3FjOtkj5Fg== X-Received: by 2002:a5d:59af:0:b0:388:c61d:4415 with SMTP id ffacd0b85a97d-3911560f325mr2216933f8f.18.1741089617020; Tue, 04 Mar 2025 04:00:17 -0800 (PST) Received: from localhost ([2a02:8308:a00c:e200::688c]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-390e4844ac6sm17312025f8f.71.2025.03.04.04.00.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Mar 2025 04:00:16 -0800 (PST) From: Andrew Jones To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: paul.walmsley@sifive.com, palmer@dabbelt.com, charlie@rivosinc.com, cleger@rivosinc.com, alex@ghiti.fr, Anup Patel , corbet@lwn.net, Alexandre Ghiti Subject: [PATCH v3 1/8] riscv: Annotate unaligned access init functions Date: Tue, 4 Mar 2025 13:00:16 +0100 Message-ID: <20250304120014.143628-11-ajones@ventanamicro.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250304120014.143628-10-ajones@ventanamicro.com> References: <20250304120014.143628-10-ajones@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250304_040018_675493_72BC8693 X-CRM114-Status: GOOD ( 10.56 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Several functions used in unaligned access probing are only run at init time. Annotate them appropriately. Fixes: f413aae96cda ("riscv: Set unaligned access speed at compile time") Reviewed-by: Alexandre Ghiti Signed-off-by: Andrew Jones --- arch/riscv/include/asm/cpufeature.h | 4 ++-- arch/riscv/kernel/traps_misaligned.c | 8 ++++---- arch/riscv/kernel/unaligned_access_speed.c | 14 +++++++------- 3 files changed, 13 insertions(+), 13 deletions(-) diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h index 569140d6e639..19defdc2002d 100644 --- a/arch/riscv/include/asm/cpufeature.h +++ b/arch/riscv/include/asm/cpufeature.h @@ -63,7 +63,7 @@ void __init riscv_user_isa_enable(void); #define __RISCV_ISA_EXT_SUPERSET_VALIDATE(_name, _id, _sub_exts, _validate) \ _RISCV_ISA_EXT_DATA(_name, _id, _sub_exts, ARRAY_SIZE(_sub_exts), _validate) -bool check_unaligned_access_emulated_all_cpus(void); +bool __init check_unaligned_access_emulated_all_cpus(void); #if defined(CONFIG_RISCV_SCALAR_MISALIGNED) void check_unaligned_access_emulated(struct work_struct *work __always_unused); void unaligned_emulation_finish(void); @@ -76,7 +76,7 @@ static inline bool unaligned_ctl_available(void) } #endif -bool check_vector_unaligned_access_emulated_all_cpus(void); +bool __init check_vector_unaligned_access_emulated_all_cpus(void); #if defined(CONFIG_RISCV_VECTOR_MISALIGNED) void check_vector_unaligned_access_emulated(struct work_struct *work __always_unused); DECLARE_PER_CPU(long, vector_misaligned_access); diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c index 7cc108aed74e..aacbd9d7196e 100644 --- a/arch/riscv/kernel/traps_misaligned.c +++ b/arch/riscv/kernel/traps_misaligned.c @@ -605,7 +605,7 @@ void check_vector_unaligned_access_emulated(struct work_struct *work __always_un kernel_vector_end(); } -bool check_vector_unaligned_access_emulated_all_cpus(void) +bool __init check_vector_unaligned_access_emulated_all_cpus(void) { int cpu; @@ -625,7 +625,7 @@ bool check_vector_unaligned_access_emulated_all_cpus(void) return true; } #else -bool check_vector_unaligned_access_emulated_all_cpus(void) +bool __init check_vector_unaligned_access_emulated_all_cpus(void) { return false; } @@ -659,7 +659,7 @@ void check_unaligned_access_emulated(struct work_struct *work __always_unused) } } -bool check_unaligned_access_emulated_all_cpus(void) +bool __init check_unaligned_access_emulated_all_cpus(void) { int cpu; @@ -684,7 +684,7 @@ bool unaligned_ctl_available(void) return unaligned_ctl; } #else -bool check_unaligned_access_emulated_all_cpus(void) +bool __init check_unaligned_access_emulated_all_cpus(void) { return false; } diff --git a/arch/riscv/kernel/unaligned_access_speed.c b/arch/riscv/kernel/unaligned_access_speed.c index 91f189cf1611..b7a8ff7ba6df 100644 --- a/arch/riscv/kernel/unaligned_access_speed.c +++ b/arch/riscv/kernel/unaligned_access_speed.c @@ -121,7 +121,7 @@ static int check_unaligned_access(void *param) return 0; } -static void check_unaligned_access_nonboot_cpu(void *param) +static void __init check_unaligned_access_nonboot_cpu(void *param) { unsigned int cpu = smp_processor_id(); struct page **pages = param; @@ -175,7 +175,7 @@ static void set_unaligned_access_static_branches(void) modify_unaligned_access_branches(&fast_and_online, num_online_cpus()); } -static int lock_and_set_unaligned_access_static_branch(void) +static int __init lock_and_set_unaligned_access_static_branch(void) { cpus_read_lock(); set_unaligned_access_static_branches(); @@ -218,7 +218,7 @@ static int riscv_offline_cpu(unsigned int cpu) } /* Measure unaligned access speed on all CPUs present at boot in parallel. */ -static int check_unaligned_access_speed_all_cpus(void) +static int __init check_unaligned_access_speed_all_cpus(void) { unsigned int cpu; unsigned int cpu_count = num_possible_cpus(); @@ -264,7 +264,7 @@ static int check_unaligned_access_speed_all_cpus(void) return 0; } #else /* CONFIG_RISCV_PROBE_UNALIGNED_ACCESS */ -static int check_unaligned_access_speed_all_cpus(void) +static int __init check_unaligned_access_speed_all_cpus(void) { return 0; } @@ -379,7 +379,7 @@ static int riscv_online_cpu_vec(unsigned int cpu) } /* Measure unaligned access speed on all CPUs present at boot in parallel. */ -static int vec_check_unaligned_access_speed_all_cpus(void *unused __always_unused) +static int __init vec_check_unaligned_access_speed_all_cpus(void *unused __always_unused) { schedule_on_each_cpu(check_vector_unaligned_access); @@ -393,13 +393,13 @@ static int vec_check_unaligned_access_speed_all_cpus(void *unused __always_unuse return 0; } #else /* CONFIG_RISCV_PROBE_VECTOR_UNALIGNED_ACCESS */ -static int vec_check_unaligned_access_speed_all_cpus(void *unused __always_unused) +static int __init vec_check_unaligned_access_speed_all_cpus(void *unused __always_unused) { return 0; } #endif -static int check_unaligned_access_all_cpus(void) +static int __init check_unaligned_access_all_cpus(void) { bool all_cpus_emulated, all_cpus_vec_unsupported;