From patchwork Mon Mar 10 15:12:11 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= X-Patchwork-Id: 14010353 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8694FC35FF2 for ; Mon, 10 Mar 2025 15:47:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Mf7nuoLPdAKaOQ5lmgawroSJ+BVHq4ix/XWFNjcEEjw=; b=CbgKb78yze462y Uz6uV0htgiu5dBHgfNYN+PyAc2Nd2RkdpyhsBVp3TaTGSqWT3EzXNo2O/F/2MoYOrSCmdfJ+d9OWI bS9HgN/zWJhvRlCA+afhY5tYADEBKhR5lEz++cYG46Z6cfnu+eIWhgGukuzjJzEJblfescOFODZCw 8fYbWmNQYdfaqTWqSF7w+RaOzJGMDfjgXMzEoVt8UGZE/CLc50lw8hNyquqWkx6lhWlFbWDO1LtDk 9+c7nZQa8WvxZ1CXWzn9o3AiwlCfB0r1MsDVJ4jfVlcE0KgMYZuQYoP0OS9y2AtRG0BIagDIDfZxi vI6ewonE1zOqeUTAOfnA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1trfLs-00000003FuY-1eUy; Mon, 10 Mar 2025 15:47:36 +0000 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1treoi-000000037Yd-3bN6 for linux-riscv@lists.infradead.org; Mon, 10 Mar 2025 15:13:21 +0000 Received: by mail-pl1-x636.google.com with SMTP id d9443c01a7336-2243803b776so68720345ad.0 for ; Mon, 10 Mar 2025 08:13:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1741619600; x=1742224400; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=iCzObjCiX22GaNtqPcn313QNcQsAxjFzTtLeQoUqwaY=; b=GadKO/aWA6LBNANRtxvkWLX+BU901uj99fPr3DezPVqVRUjP/xBRg26U6L5iY4Jq6c 3I6G2Xt3F4x/lWVCT4IQQP9YYWNBFEPs8JH8CtBZkJCGkfs3wBzt4arGwi/vZxuoDX9x NKbkOzJWA3dSQV8R9iM3m758Wad4ckgjtXOScRpEauKJl+vCywuanQDB3OqUae5uc0TE jLYF+JDRlqeohSXOEmtGZ9wvbV1EZ1rD/hy/8e9xD4uGHwBiWxFi2HuGWi1q1NLQe5Vl A9nf7MSnURWG0pXFtkNaHYe5gcJVbZ6yF43kgYxVBDtKVuPrKq+CS/ynm6Uj7Xm3XNqg J1Tw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741619600; x=1742224400; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=iCzObjCiX22GaNtqPcn313QNcQsAxjFzTtLeQoUqwaY=; b=GXmYS76uqmpSc6OfhnYUG8fPxwAgoz3dP7oCxymTndZq+Yb0mbGxu+KrySZyTw+khF /GYioPQs9+lKu8uSujjHRPSJ3pRhX2lRoUFgVUB31zOAqujjYwmafG1JWYEBHOdKa3f4 wS7WteuE5Nb3uaxnfvRffcRPm1x5izVqH2jROe5gwxvI3tj6VpiaJWFDOQpQWpXWOjlh P1p9rUjeI+weatE5Jeiw47YKXE53QpBb2qSaE7DkXHFnZL0ByjEbPuhYCkVk+VhSZw3D E1GiYd5/hjc/LZTubZ2ONTqNauSCexRaIgTMOsWHU0W4Qxc+YZ6/Ktrlblzk6ZRWTQWZ fNtg== X-Forwarded-Encrypted: i=1; AJvYcCWTc9X7zyNh/Cy6mi4L12kFQxidBSe1M34npgyGJ7pEJhh6G5Em8Dx8t60dO0r+3/TQEzhho4ID/BxadA==@lists.infradead.org X-Gm-Message-State: AOJu0Yw9HLONh75OfWLn/TZhzQTcfeBggEyf+mqGhFoIKsgky9HigWYU Xc8VZ7VE96sXxFvf7KzTdFf/gjDXO5YmSDfoWOlGIbBGe96REHkhH2HEoT8U/m4= X-Gm-Gg: ASbGncuDju+qhWBCzhbOszxaSUxf2qGs24D2DfsABYzQLYkqpLQhKk/wwRD2M2kYOn4 t7+bUsKbWRY7Jt4uNM7VNtTq7Z/akX2f3eBgEAUBWdMQZDmEJPdqfJo2daR3REE8+/paI7EnUDX voDd1z+TqopLzGoR9/ZuX9RIXVWA1wqy+aLRst+vfRc2p3pl7wi1qR9/AWdgR6Si+amd8BlIEdA NAOT44A6r1f4d+hcs/fdMOYuHvmapJTfM4fTkqr9eyqYbqtqcGtwTOic4K7iAHPM8cnLbxsEboH iXYgncxwyZNU3a245Yqbjrr5YFUQJllysNn35tdMqterEw== X-Google-Smtp-Source: AGHT+IFAN+g28xsEl6cRHjCuf/iafyl8QjCyWFLr5ynPSsnxM9bGhegkupQZbu72YeMxbfX8Ebj7iA== X-Received: by 2002:a17:903:32c5:b0:224:10a2:cad5 with SMTP id d9443c01a7336-2242887b36bmr234821365ad.10.1741619600386; Mon, 10 Mar 2025 08:13:20 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-224109e99dfsm79230515ad.91.2025.03.10.08.13.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Mar 2025 08:13:19 -0700 (PDT) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: Paul Walmsley , Palmer Dabbelt , Anup Patel , Atish Patra , Shuah Khan , Jonathan Corbet , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Samuel Holland Subject: [PATCH v3 04/17] riscv: misaligned: request misaligned exception from SBI Date: Mon, 10 Mar 2025 16:12:11 +0100 Message-ID: <20250310151229.2365992-5-cleger@rivosinc.com> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250310151229.2365992-1-cleger@rivosinc.com> References: <20250310151229.2365992-1-cleger@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250310_081320_904411_EE5C9C37 X-CRM114-Status: GOOD ( 16.82 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Now that the kernel can handle misaligned accesses in S-mode, request misaligned access exception delegation from SBI. This uses the FWFT SBI extension defined in SBI version 3.0. Signed-off-by: Clément Léger Reviewed-by: Andrew Jones --- arch/riscv/include/asm/cpufeature.h | 3 +- arch/riscv/kernel/traps_misaligned.c | 77 +++++++++++++++++++++- arch/riscv/kernel/unaligned_access_speed.c | 11 +++- 3 files changed, 86 insertions(+), 5 deletions(-) diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h index 569140d6e639..ad7d26788e6a 100644 --- a/arch/riscv/include/asm/cpufeature.h +++ b/arch/riscv/include/asm/cpufeature.h @@ -64,8 +64,9 @@ void __init riscv_user_isa_enable(void); _RISCV_ISA_EXT_DATA(_name, _id, _sub_exts, ARRAY_SIZE(_sub_exts), _validate) bool check_unaligned_access_emulated_all_cpus(void); +void unaligned_access_init(void); +int cpu_online_unaligned_access_init(unsigned int cpu); #if defined(CONFIG_RISCV_SCALAR_MISALIGNED) -void check_unaligned_access_emulated(struct work_struct *work __always_unused); void unaligned_emulation_finish(void); bool unaligned_ctl_available(void); DECLARE_PER_CPU(long, misaligned_access_speed); diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c index 7cc108aed74e..90ac74191357 100644 --- a/arch/riscv/kernel/traps_misaligned.c +++ b/arch/riscv/kernel/traps_misaligned.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #define INSN_MATCH_LB 0x3 @@ -635,7 +636,7 @@ bool check_vector_unaligned_access_emulated_all_cpus(void) static bool unaligned_ctl __read_mostly; -void check_unaligned_access_emulated(struct work_struct *work __always_unused) +static void check_unaligned_access_emulated(struct work_struct *work __always_unused) { int cpu = smp_processor_id(); long *mas_ptr = per_cpu_ptr(&misaligned_access_speed, cpu); @@ -646,6 +647,13 @@ void check_unaligned_access_emulated(struct work_struct *work __always_unused) __asm__ __volatile__ ( " "REG_L" %[tmp], 1(%[ptr])\n" : [tmp] "=r" (tmp_val) : [ptr] "r" (&tmp_var) : "memory"); +} + +static int cpu_online_check_unaligned_access_emulated(unsigned int cpu) +{ + long *mas_ptr = per_cpu_ptr(&misaligned_access_speed, cpu); + + check_unaligned_access_emulated(NULL); /* * If unaligned_ctl is already set, this means that we detected that all @@ -654,9 +662,10 @@ void check_unaligned_access_emulated(struct work_struct *work __always_unused) */ if (unlikely(unaligned_ctl && (*mas_ptr != RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED))) { pr_crit("CPU misaligned accesses non homogeneous (expected all emulated)\n"); - while (true) - cpu_relax(); + return -EINVAL; } + + return 0; } bool check_unaligned_access_emulated_all_cpus(void) @@ -688,4 +697,66 @@ bool check_unaligned_access_emulated_all_cpus(void) { return false; } +static int cpu_online_check_unaligned_access_emulated(unsigned int cpu) +{ + return 0; +} #endif + +#ifdef CONFIG_RISCV_SBI + +static bool misaligned_traps_delegated; + +static int cpu_online_sbi_unaligned_setup(unsigned int cpu) +{ + if (sbi_fwft_set(SBI_FWFT_MISALIGNED_EXC_DELEG, 1, 0) && + misaligned_traps_delegated) { + pr_crit("Misaligned trap delegation non homogeneous (expected delegated)"); + return -EINVAL; + } + + return 0; +} + +static void unaligned_sbi_request_delegation(void) +{ + int ret; + + ret = sbi_fwft_all_cpus_set(SBI_FWFT_MISALIGNED_EXC_DELEG, 1, 0, 0); + if (ret) + return; + + misaligned_traps_delegated = true; + pr_info("SBI misaligned access exception delegation ok\n"); + /* + * Note that we don't have to take any specific action here, if + * the delegation is successful, then + * check_unaligned_access_emulated() will verify that indeed the + * platform traps on misaligned accesses. + */ +} + +void unaligned_access_init(void) +{ + if (sbi_probe_extension(SBI_EXT_FWFT) > 0) + unaligned_sbi_request_delegation(); +} +#else +void unaligned_access_init(void) {} + +static int cpu_online_sbi_unaligned_setup(unsigned int cpu __always_unused) +{ + return 0; +} +#endif + +int cpu_online_unaligned_access_init(unsigned int cpu) +{ + int ret; + + ret = cpu_online_sbi_unaligned_setup(cpu); + if (ret) + return ret; + + return cpu_online_check_unaligned_access_emulated(cpu); +} diff --git a/arch/riscv/kernel/unaligned_access_speed.c b/arch/riscv/kernel/unaligned_access_speed.c index 91f189cf1611..2f3aba073297 100644 --- a/arch/riscv/kernel/unaligned_access_speed.c +++ b/arch/riscv/kernel/unaligned_access_speed.c @@ -188,13 +188,20 @@ arch_initcall_sync(lock_and_set_unaligned_access_static_branch); static int riscv_online_cpu(unsigned int cpu) { + int ret; static struct page *buf; /* We are already set since the last check */ if (per_cpu(misaligned_access_speed, cpu) != RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN) goto exit; - check_unaligned_access_emulated(NULL); + ret = cpu_online_unaligned_access_init(cpu); + if (ret) + return ret; + + if (per_cpu(misaligned_access_speed, cpu) == RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED) + goto exit; + buf = alloc_pages(GFP_KERNEL, MISALIGNED_BUFFER_ORDER); if (!buf) { pr_warn("Allocation failure, not measuring misaligned performance\n"); @@ -403,6 +410,8 @@ static int check_unaligned_access_all_cpus(void) { bool all_cpus_emulated, all_cpus_vec_unsupported; + unaligned_access_init(); + all_cpus_emulated = check_unaligned_access_emulated_all_cpus(); all_cpus_vec_unsupported = check_vector_unaligned_access_emulated_all_cpus();