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d=google.com; s=20230601; t=1741636525; x=1742241325; darn=lists.infradead.org; h=to:from:subject:message-id:references:mime-version:in-reply-to:date :from:to:cc:subject:date:message-id:reply-to; bh=Mtw5A6pnErP63NBf+2oMOxljRBPUk1W+HOiO6no4Q+Y=; b=usk9jXiA8ZPZOBnI08OaUXGD5kujUGLSugQedEvOR9mKR1JcGItY8AZIk8gWoWQV+i xXCilVvSYRZ+K1C9fyBBzEvobYN1Ho16JOisc+clpyRDdibK8GZJbeEYxvggUGdqLgjs UNU63dYIr89VNc4P5owlx86O6uwZOvxepZAgn/E2LXcH0QWhvGPGKusxX+IH8xcjXgoE OiKizXA3eDL81e2QP/s9eiMhBCw7DSCXOzmvXhwbkQweXUWT+05E427unCFZXYuw4p4u i09dI8NzirsIkY9+qWoBR7+w+ItpsIQxTqdNstqNtLyI6F/qh2aiFA/svMSWh5yZY+vO 0HNQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741636525; x=1742241325; h=to:from:subject:message-id:references:mime-version:in-reply-to:date :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=Mtw5A6pnErP63NBf+2oMOxljRBPUk1W+HOiO6no4Q+Y=; b=IJG+Yr2Ty361jDFvIqPy3pT4vioMVkjzZoN793nq9FTg7vZXJWqbxY9mj7wjB3GkzL qTY9gtyN/p+ptU+4wLogL1petUGVK63sDbTEQwIZGEkrvGyMEWHTGNh03HGtCl0tAVgG lVigYuUlnywQpAUhUcwLtIpRq9nvUV0glNkieh9a5MILwxFnDsz01BCHJVmJyA/7B+Cm LuXpwe41ypvd9Wcy4S8+D8GaUi8su3QwFG2SKckwU4KOUe4OxLpJBCsGOeAZbWEjgxCD Y2wBR0TLcoJP7VSZG6aKuvurNCrGPfp5a2oGmaK8aSOxpBT0XoT91Re7zRdbwuepjMlf bIgw== X-Forwarded-Encrypted: i=1; AJvYcCXe25DKqjJ564wRMXGRPS3GQ9JL7pkiOf0LysPIDkFHnDh1xw51KePlYFyF5DVU3m3BJrPQnnDfUsbqpg==@lists.infradead.org X-Gm-Message-State: AOJu0Yye+axYo+VrD0+bdnBvYnN/Xdy/oRZm/B7vPH3T/X8FWTCTHTWc fcsGjqmlUQ+5x8EUZwS325LWn3/+ESPU7rnFAS6elqsYm8+ZJi2zAaNkAkqlNUDnLTMbf7fLp/D 20lcrLg== X-Google-Smtp-Source: AGHT+IFGWlShb5kIWxI+81Al+aKaRpPgOqN7dElfZLMAJXDNRxxbs9Dr7UEPZnwpTE1mHFFuj6jma5OrHpr5 X-Received: from pllo19.prod.google.com ([2002:a17:902:7793:b0:223:5a6e:b17]) (user=irogers job=prod-delivery.src-stubby-dispatcher) by 2002:a17:903:32c6:b0:224:13c0:58e3 with SMTP id d9443c01a7336-22428bf1976mr198632485ad.51.1741636525408; Mon, 10 Mar 2025 12:55:25 -0700 (PDT) Date: Mon, 10 Mar 2025 12:55:17 -0700 In-Reply-To: <20250310195518.2012571-1-irogers@google.com> Mime-Version: 1.0 References: <20250310195518.2012571-1-irogers@google.com> X-Mailer: git-send-email 2.49.0.rc0.332.g42c0ae87b1-goog Message-ID: <20250310195518.2012571-2-irogers@google.com> Subject: [PATCH v1 1/2] perf parse-events: Make legacy events always have priority over sysfs/json From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , Paul Walmsley , Palmer Dabbelt , Albert Ou , James Clark , Dominique Martinet , Yang Jihong , Yang Li , Weilin Wang , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Leo Yan X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250310_125527_042691_C32AF142 X-CRM114-Status: GOOD ( 24.41 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org This reverts the behavior of commit a24d9d9dc096 ("perf parse-events: Make legacy events lower priority than sysfs/JSON"). That commit states: As part of that report Mark Rutland requested that legacy events not be higher in priority when a PMU is specified reversing what has until this change been perf's default behavior. with an Acked-by: Mark Rutland tag. Mark expresses this preference here: https://lore.kernel.org/lkml/ZVzXjz_0nYbmSGPQ@FVFF77S0Q05N.cambridge.arm.com/ On an Alderlake this commit caused `cpu_core/instructions/` to be encoded as: ------------------------------------------------------------ perf_event_attr: type 4 (cpu_core) size 136 config 0xc0 (instructions) sample_type IDENTIFIER read_format TOTAL_TIME_ENABLED|TOTAL_TIME_RUNNING disabled 1 inherit 1 enable_on_exec 1 exclude_guest 1 ------------------------------------------------------------ While `instructions` would be encoded as: ------------------------------------------------------------ perf_event_attr: type 0 (PERF_TYPE_HARDWARE) size 136 config 0x400000001 sample_type IDENTIFIER read_format TOTAL_TIME_ENABLED|TOTAL_TIME_RUNNING disabled 1 inherit 1 enable_on_exec 1 exclude_guest 1 ------------------------------------------------------------ As the event parsing for legacy events uses parse_events_add_numeric, rather than the more generic PMU handling case, we end up with the same event name being encoded two ways. However, as instructions is also a cpu_atom event on Alderlake, or any hybrid system, the PMU prefixes are added in the stat output meaning instructions is reported as cpu_core/instructions/ and cpu_atom/instructions/ even though those events are encoded differently and potentially have different behaviors. We shouldn't be having the same event with two different encodings and I followed up the commit with changing the prioritization of legacy events also when no PMU is specified in commit 617824a7f0f7 ("perf parse-events: Prefer sysfs/JSON hardware events over legacy"). RISC-V have been asking that legacy events also be a lower priority than sysfs/json to avoid driver complexity. They've since had to work around this issue meaning it isn't a necessity: If the overriding legacy with JSON is available, each future vendor may just provide the json file instead of modifying the driver. However, it will be a matter of convenience and clutter free future rather than a necessity at this point. https://lists.riscv.org/g/sig-perf-analysis/topic/110906276#msg458 Landing the commit making encoding consistent and having sysfs/json a priority has been pushed back against by Namhyung Kim, Arnaldo Carvalho de Melo and James Clark. James assert the ARM drivers are now fixed and don't need the prioritization. RISC-V's interests have been ignored. The fact that legacy events are antiquated, imprecise in meaning, brittle, misleading and don't give us a way to fix kernel issues in software, have also been ignored: https://lore.kernel.org/lkml/Z8sMcta0zTWeOso4@x1/ Given the push back against sysfs/json being a priority, contrary to Mark Rutland's insistence this was the sensible way to do things, contrary to RISC-V's wishes, and contrary to my own preference that legacy events do become legacy, this patch changes the priority back to legacy events being the priority consistently - that is instructions and cpu_core/instructions/ are both encoded using legacy events. It isn't a straight revert as clean-ups/refactorings are kept in place. Signed-off-by: Ian Rogers --- tools/perf/tests/parse-events.c | 13 +++---------- tools/perf/util/parse-events.c | 26 +++++++++----------------- 2 files changed, 12 insertions(+), 27 deletions(-) diff --git a/tools/perf/tests/parse-events.c b/tools/perf/tests/parse-events.c index 5ec2e5607987..78e8ae825bf8 100644 --- a/tools/perf/tests/parse-events.c +++ b/tools/perf/tests/parse-events.c @@ -162,16 +162,9 @@ static int test__checkevent_numeric(struct evlist *evlist) static int assert_hw(struct perf_evsel *evsel, enum perf_hw_id id, const char *name) { - struct perf_pmu *pmu; - - if (evsel->attr.type == PERF_TYPE_HARDWARE) { - TEST_ASSERT_VAL("wrong config", test_perf_config(evsel, id)); - return 0; - } - pmu = perf_pmus__find_by_type(evsel->attr.type); - - TEST_ASSERT_VAL("unexpected PMU type", pmu); - TEST_ASSERT_VAL("PMU missing event", perf_pmu__have_event(pmu, name)); + TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE == evsel->attr.type); + TEST_ASSERT_VAL("wrong config", test_perf_config(evsel, id)); + TEST_ASSERT_VAL("wrong name", !strcmp(evsel__hw_names[id], name)); return 0; } diff --git a/tools/perf/util/parse-events.c b/tools/perf/util/parse-events.c index 35e48fe56dfa..04bb70ba4292 100644 --- a/tools/perf/util/parse-events.c +++ b/tools/perf/util/parse-events.c @@ -1023,12 +1023,10 @@ static int config_term_pmu(struct perf_event_attr *attr, return -EINVAL; } /* - * Rewrite the PMU event to a legacy cache one unless the PMU - * doesn't support legacy cache events or the event is present - * within the PMU. + * Rewrite the PMU event to a legacy cache one as legacy events + * take priority over sysfs/json. */ - if (perf_pmu__supports_legacy_cache(pmu) && - !perf_pmu__have_event(pmu, term->config)) { + if (perf_pmu__supports_legacy_cache(pmu)) { attr->type = PERF_TYPE_HW_CACHE; return parse_events__decode_legacy_cache(term->config, pmu->type, &attr->config); @@ -1049,19 +1047,13 @@ static int config_term_pmu(struct perf_event_attr *attr, return -EINVAL; } /* - * If the PMU has a sysfs or json event prefer it over - * legacy. ARM requires this. + * Rewrite the PMU event to a legacy cache one as legacy events + * take priority over sysfs/json. */ - if (perf_pmu__have_event(pmu, term->config)) { - term->type_term = PARSE_EVENTS__TERM_TYPE_USER; - term->no_value = true; - term->alternate_hw_config = true; - } else { - attr->type = PERF_TYPE_HARDWARE; - attr->config = term->val.num; - if (perf_pmus__supports_extended_type()) - attr->config |= (__u64)pmu->type << PERF_PMU_TYPE_SHIFT; - } + attr->type = PERF_TYPE_HARDWARE; + attr->config = term->val.num; + if (perf_pmus__supports_extended_type()) + attr->config |= (__u64)pmu->type << PERF_PMU_TYPE_SHIFT; return 0; } if (term->type_term == PARSE_EVENTS__TERM_TYPE_USER ||