From patchwork Mon Mar 17 17:06:09 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= X-Patchwork-Id: 14019752 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A3A45C35FFB for ; Mon, 17 Mar 2025 17:13:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Vb7SbCv9WR/TIuIrUmp6gUN3pEPFMvPRGXLbDTBbLi0=; b=dCy+Y+67cs5SBj Z/zjKEMUJY8hKqqTHgrL1Sh5Tw15K2pHOeNIYchWIl5rvdz2ZCM7UQqThIdscqVFMIK9gOOPilMOU WYSizhdhe3TXTHjsl9f3Vztoi9P+9Qz21WdfTzv3dGyJm1SGqlIbAHoLx+uAgPjIRozY/B2bIBOkI Jd8Jbf6+keaq3cPHr2WQIGsAbxh3cmNrYRBYdZn3+PlcNZkUQ2WXQn96VTzebxaXfiR/zV3iK4KNC BOMe08Pej0l1mw1WiIExSntjJun9MAccarWvjsV0xWw7P6WR/zMohmsUI/f8KamC/cSkLVIkuNdqn aLTkX8KyAdn+FhfBBm2A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tuE1N-00000003UtZ-0lVH; Mon, 17 Mar 2025 17:13:01 +0000 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tuDwh-00000003TNy-2Muk for linux-riscv@lists.infradead.org; Mon, 17 Mar 2025 17:08:12 +0000 Received: by mail-wm1-x336.google.com with SMTP id 5b1f17b1804b1-4394a0c65fcso22361105e9.1 for ; Mon, 17 Mar 2025 10:08:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1742231290; x=1742836090; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WzyfmLdoy3J2d7N3ElT+BcY4glWrhhZZ3MI8rtjNdBk=; b=PC8SMDxg/39rRwF1oy1T82SRYA2SGjrhRwlzN1MOTDWf6EhinxEeepattelVs5vRsS dBF9AzjVS1EivyFXbQ8QVkKgM/phpL2JX5k3Tk76Us4kBqj7ebyBSAXz3Q9+NLAXEtTK jfspf0XDaMHsz4FzzFIG/1d50kic6VbkFAC2717M2C3D3tsKEZwxetGv+A+BmX+2H1Fb 36fDXAbn79rBcBxy+zni/kmQjJwEvvuQwlSGl2w2yxnOose072tPUhEC7qJZhqhS7i5I 5k1xS1BkIBoJ1Ja9ItyNqmiQN+WMx4hgDLW/x/lnDMVviBBxQdeJS7P5XnN7K/C+xMeY V4oA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1742231290; x=1742836090; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WzyfmLdoy3J2d7N3ElT+BcY4glWrhhZZ3MI8rtjNdBk=; b=o8Kg4IgtU/gws1mEZrECUattWePaqQXT6+ysiYq/Tw4Df0JMZYdrsiUl0GgwMp02Xg b8ZGl1BI+iyE7TtoLes0oCWP17C8eawSXkd1cMt4tjlU8ioJgvSVa35x3XIPI+AwyC8X OQISG6Upb39IuBcejODzJ+0wTH35sYB3kZP29vx84osO+iK8ZUmmx++mseU/dF6adZRb pppWobq134kPyMYqhfEAidMQSjGafw5Cif0WgGyOCCAoddltGwPxTs/s4mM1RuOCA9oc VmCn1dQtBOCvX9viQudE43yYW/2pHnq9g/Nqqd+0sUZ+mrbHzD02NqP/g/tTUgD3+rRL DmkA== X-Forwarded-Encrypted: i=1; AJvYcCXcT/eb/koFF/8uSXl58NtElZagOy7tkwJftMcvTDaRZWFORv+Np85eB3QaRGKqe1HkLkkdnocKmkIl0Q==@lists.infradead.org X-Gm-Message-State: AOJu0Yz4EMgJn684AbJRWdLoqylvFdp2D76aStY9UmSJ08E8rX8NQgE3 oJpEu5hyHjiIUb/+erbDxrv9cKg/myPVgomkg2qfXpQoNCfD2HWZdn1Bc5eKD5U= X-Gm-Gg: ASbGncuB7bsrdVfhPfbO9KO4WcM0YBwKIvSdmLzlhRnxwvQ6JageogOENabfveVcmzv QAeCacDKiMoXy7/L2yPAeL3LzV22ef+f/ny579bB1vrg5GBYWsHm4RzsicemXRtkAP/Z+fe1Umt zcWXkm2W0GJwZipE9jqRoT05hfuDLxp6+R7wEua/ROWdlRy77jqzcU7Y4euPAg9HEMehRnzgQRX DdatoqtlQksaKcLYHLXt2GXMoCRY+5MEJsAwitWObOSlX9Gkztufb0cE3Y2tYGPnf6X4reHVPkg WtMpjdjlwbf0mEnkyc4DxQZYyrgWMlmgDFkFJkBzaZCbhA== X-Google-Smtp-Source: AGHT+IEXtMD53rpT5+I6qBlek794Ca+55Nd9V0KPjs7YD1xcg1pmEqFLjYcNNVWjDAHYDrYaGY3dSQ== X-Received: by 2002:a05:600c:3c89:b0:43c:f87c:24ce with SMTP id 5b1f17b1804b1-43d1ecd7adfmr118223885e9.21.1742231290211; Mon, 17 Mar 2025 10:08:10 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d23cddb2asm96014505e9.39.2025.03.17.10.08.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Mar 2025 10:08:09 -0700 (PDT) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: Paul Walmsley , Palmer Dabbelt , Anup Patel , Atish Patra , Shuah Khan , Jonathan Corbet , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Samuel Holland , Andrew Jones Subject: [PATCH v4 03/18] riscv: sbi: add FWFT extension interface Date: Mon, 17 Mar 2025 18:06:09 +0100 Message-ID: <20250317170625.1142870-4-cleger@rivosinc.com> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250317170625.1142870-1-cleger@rivosinc.com> References: <20250317170625.1142870-1-cleger@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250317_100811_626421_1A0E5859 X-CRM114-Status: GOOD ( 13.74 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org This SBI extensions enables supervisor mode to control feature that are under M-mode control (For instance, Svadu menvcfg ADUE bit, Ssdbltrp DTE, etc). Add an interface to set local features for a specific cpu mask as well as for the online cpu mask. Signed-off-by: Clément Léger Reviewed-by: Andrew Jones --- arch/riscv/include/asm/sbi.h | 20 +++++++++++ arch/riscv/kernel/sbi.c | 69 ++++++++++++++++++++++++++++++++++++ 2 files changed, 89 insertions(+) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index d11d22717b49..1cecfa82c2e5 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -503,6 +503,26 @@ int sbi_remote_hfence_vvma_asid(const struct cpumask *cpu_mask, unsigned long asid); long sbi_probe_extension(int ext); +int sbi_fwft_local_set_cpumask(const cpumask_t *mask, u32 feature, + unsigned long value, unsigned long flags); +/** + * sbi_fwft_local_set() - Set a feature on all online cpus + * @feature: The feature to be set + * @value: The feature value to be set + * @flags: FWFT feature set flags + * + * Return: 0 on success, appropriate linux error code otherwise. + */ + static inline int sbi_fwft_local_set(u32 feature, unsigned long value, + unsigned long flags) + { + return sbi_fwft_local_set_cpumask(cpu_online_mask, feature, value, + flags); + } + +int sbi_fwft_get(u32 feature, unsigned long *value); +int sbi_fwft_set(u32 feature, unsigned long value, unsigned long flags); + /* Check if current SBI specification version is 0.1 or not */ static inline int sbi_spec_is_0_1(void) { diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c index 1989b8cade1b..d41a5642be24 100644 --- a/arch/riscv/kernel/sbi.c +++ b/arch/riscv/kernel/sbi.c @@ -299,6 +299,75 @@ static int __sbi_rfence_v02(int fid, const struct cpumask *cpu_mask, return 0; } +/** + * sbi_fwft_get() - Get a feature for the local hart + * @feature: The feature ID to be set + * @value: Will contain the feature value on success + * + * Return: 0 on success, appropriate linux error code otherwise. + */ +int sbi_fwft_get(u32 feature, unsigned long *value) +{ + return -EOPNOTSUPP; +} + +/** + * sbi_fwft_set() - Set a feature on the local hart + * @feature: The feature ID to be set + * @value: The feature value to be set + * @flags: FWFT feature set flags + * + * Return: 0 on success, appropriate linux error code otherwise. + */ +int sbi_fwft_set(u32 feature, unsigned long value, unsigned long flags) +{ + return -EOPNOTSUPP; +} + +struct fwft_set_req { + u32 feature; + unsigned long value; + unsigned long flags; + atomic_t error; +}; + +static void cpu_sbi_fwft_set(void *arg) +{ + struct fwft_set_req *req = arg; + int ret; + + ret = sbi_fwft_set(req->feature, req->value, req->flags); + if (ret) + atomic_set(&req->error, ret); +} + +/** + * sbi_fwft_local_set() - Set a feature for the specified cpumask + * @mask: CPU mask of cpus that need the feature to be set + * @feature: The feature ID to be set + * @value: The feature value to be set + * @flags: FWFT feature set flags + * + * Return: 0 on success, appropriate linux error code otherwise. + */ +int sbi_fwft_local_set_cpumask(const cpumask_t *mask, u32 feature, + unsigned long value, unsigned long flags) +{ + struct fwft_set_req req = { + .feature = feature, + .value = value, + .flags = flags, + .error = ATOMIC_INIT(0), + }; + + if (feature & SBI_FWFT_GLOBAL_FEATURE_BIT) + return -EINVAL; + + on_each_cpu_mask(mask, cpu_sbi_fwft_set, &req, 1); + + return atomic_read(&req.error); +} + /** * sbi_set_timer() - Program the timer for next timer event. * @stime_value: The value after which next timer event should fire.