From patchwork Mon Mar 17 17:06:11 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= X-Patchwork-Id: 14019755 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D443CC35FFC for ; Mon, 17 Mar 2025 17:13:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=cinsuHuOYavEntm8uvEJiUGWRcxHzPUrsTEUj6CzbTQ=; b=Ps3EMF31aFjn6C LDIwRNFfh5pxGQf0Fm6XkaOA5D1czt8oJ1f+i7tsunHOw3LX7pSQk57eO2LKXZgeqBxgMgCI/2mCQ c9yIoF8bYad5r5k3ioUS1t3DtK9z9D22xhCyGTJ+N7tYC2KOGmAWMU/hXGNVxV8dkmlH485XFuM7X AfXbZjU2kyTHSNDh4V4YiC/Tm/he4AdfBF4qjzNicPjqwuxRU1dOSs+HYpmqo7ccHkSbf7GfUaiGQ x99nqk92CJoigFV3gUgIWLiuon+j7TNi9D4EWDqHdRjlNJ5ay/9P8obQEeV3RsBXc9EPHCENZ1XkE gYNuTpw8IFRecOvQWx7A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tuE1P-00000003Uvf-1HN1; Mon, 17 Mar 2025 17:13:03 +0000 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tuDwk-00000003TQ6-00GU for linux-riscv@lists.infradead.org; Mon, 17 Mar 2025 17:08:15 +0000 Received: by mail-wm1-x32c.google.com with SMTP id 5b1f17b1804b1-43cef035a3bso17141405e9.1 for ; Mon, 17 Mar 2025 10:08:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1742231293; x=1742836093; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5k1emOUih8WEclNZ1DDbkx/NdClZ1In2F+3XrsHVDoI=; b=yfnibR/2sqg/hjS1TqiOgjyd32Mo01AVE9b498yRTklo3g/8sglkv2/X1MBDozUxD2 3nW7Lmm3Dl/LzRkk49zR5ZAytTS4uFk0hUlLL6FqyFkStS0RYWujs0Ycmf6fQmPHmwQZ KcxH5x8r2KVqR0fF12v8zkWs9gxz2KM8mN//ZNsmCX9A6jQF1Lux/HIEVeQwPKJGKRnK dT/zHfGvMFB6Vl9VOfY/3QbtyuBBRi/xz/hiKoNXAKixyp1s3MthhL+cCRtLBoquiFqU NyNz1l+6Zq+qj2sCLqBk/IVBGTc6eWyxQ0WcVmKmk6Pyvk7lac7GjO89lnjiG3lPjU5K YHzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1742231293; x=1742836093; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5k1emOUih8WEclNZ1DDbkx/NdClZ1In2F+3XrsHVDoI=; b=HDWG+0uy69+PbaJXn0J+68ZVyBZaPZbTACfCAhmQzXo3Dt4K2Da93h1dwd4jZkURq/ yHHlE30i08sQQ0UBoGVvJ3Ik9l+iX/lUmU9tKZyKEHce2+Q8XnVQyL6mubpJ18rRK6iO 9PlueAKgC+VEgY2SWfyKJgnHzfWvcrV+HQIF6tdq0HXKh6G3ZXcY52NX9wohUnwolPpp 4UJ1ZGCJtIb0D2UDMaR8IKo+DFQrCm1ZQG0Ssy6AxIJshVtt5QNyxwOb2MSaiZML5s9U V4boRC8VGx+QRL0X63Hrpq529q20ITgdOMFEbcB8ok/l792H0pwPmHV7q2Bj5eyKf3Ki c4rQ== X-Forwarded-Encrypted: i=1; AJvYcCVFG5WCEnhsWnebVjAAfh8wNoje9bqu5xMFzJr2p1RjrANQNr6I21UrKNZyayJtbt194euybichB32pgQ==@lists.infradead.org X-Gm-Message-State: AOJu0YzYgsobQ4xQkp5EeqDiDbtOXXNxgbqkMeT8hW2G5hRIKrM7l/nb 6M9c1k0c2ErYxyoSyiUj2XE5+uGSOmOwMCgAMOutv9x6zHQzZABcUo+6692k1ioyupNyHeFvUg3 NQDs= X-Gm-Gg: ASbGncs0blgxmRvC12cYyAcwRK6+0lXw+MdZgA1UiCDazZgKxlE+gnt/l+Mv0ywjf7e KnHgFNNuz5Ya2NTTAavF9mlyllhf+jqM5Uml6XXkh/P9tVzeek5HlwsgCb3LOVfsdDYPGsHi1e9 q6SZ0g2rzAIsLbtZ/CV6fnVarClQx850lPPH/OmaC7Iwz1EMEzmLQmvVOyyPfCDR1y4psCo7anf 4eKM+ewXksuCRDNgM73s3wytgoT45GIrx5lD+TKn2E23Za9ULORkcAHvbApvsDcyER+m6SUtqo4 t/SKWP6L+rsf3H4odHZAqi7A+SbRU3Thnhg+/NWnJw902Q== X-Google-Smtp-Source: AGHT+IGirZlNuMI7AkYZLJxITsbB2mx0iqkOoTwEVui95+l6OuB5d7SYtKlA2CI4i4rX//+fE8Z8jQ== X-Received: by 2002:a05:600c:468a:b0:43c:fb36:d296 with SMTP id 5b1f17b1804b1-43d1ed0e03dmr115529165e9.25.1742231292646; Mon, 17 Mar 2025 10:08:12 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d23cddb2asm96014505e9.39.2025.03.17.10.08.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Mar 2025 10:08:11 -0700 (PDT) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: Paul Walmsley , Palmer Dabbelt , Anup Patel , Atish Patra , Shuah Khan , Jonathan Corbet , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Samuel Holland , Andrew Jones Subject: [PATCH v4 05/18] riscv: misaligned: request misaligned exception from SBI Date: Mon, 17 Mar 2025 18:06:11 +0100 Message-ID: <20250317170625.1142870-6-cleger@rivosinc.com> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250317170625.1142870-1-cleger@rivosinc.com> References: <20250317170625.1142870-1-cleger@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250317_100814_048773_95A7F9A0 X-CRM114-Status: GOOD ( 16.46 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Now that the kernel can handle misaligned accesses in S-mode, request misaligned access exception delegation from SBI. This uses the FWFT SBI extension defined in SBI version 3.0. Signed-off-by: Clément Léger Reviewed-by: Andrew Jones --- arch/riscv/include/asm/cpufeature.h | 3 +- arch/riscv/kernel/traps_misaligned.c | 77 +++++++++++++++++++++- arch/riscv/kernel/unaligned_access_speed.c | 11 +++- 3 files changed, 86 insertions(+), 5 deletions(-) diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h index 569140d6e639..ad7d26788e6a 100644 --- a/arch/riscv/include/asm/cpufeature.h +++ b/arch/riscv/include/asm/cpufeature.h @@ -64,8 +64,9 @@ void __init riscv_user_isa_enable(void); _RISCV_ISA_EXT_DATA(_name, _id, _sub_exts, ARRAY_SIZE(_sub_exts), _validate) bool check_unaligned_access_emulated_all_cpus(void); +void unaligned_access_init(void); +int cpu_online_unaligned_access_init(unsigned int cpu); #if defined(CONFIG_RISCV_SCALAR_MISALIGNED) -void check_unaligned_access_emulated(struct work_struct *work __always_unused); void unaligned_emulation_finish(void); bool unaligned_ctl_available(void); DECLARE_PER_CPU(long, misaligned_access_speed); diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c index 7cc108aed74e..fa7f100b95bd 100644 --- a/arch/riscv/kernel/traps_misaligned.c +++ b/arch/riscv/kernel/traps_misaligned.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #define INSN_MATCH_LB 0x3 @@ -635,7 +636,7 @@ bool check_vector_unaligned_access_emulated_all_cpus(void) static bool unaligned_ctl __read_mostly; -void check_unaligned_access_emulated(struct work_struct *work __always_unused) +static void check_unaligned_access_emulated(struct work_struct *work __always_unused) { int cpu = smp_processor_id(); long *mas_ptr = per_cpu_ptr(&misaligned_access_speed, cpu); @@ -646,6 +647,13 @@ void check_unaligned_access_emulated(struct work_struct *work __always_unused) __asm__ __volatile__ ( " "REG_L" %[tmp], 1(%[ptr])\n" : [tmp] "=r" (tmp_val) : [ptr] "r" (&tmp_var) : "memory"); +} + +static int cpu_online_check_unaligned_access_emulated(unsigned int cpu) +{ + long *mas_ptr = per_cpu_ptr(&misaligned_access_speed, cpu); + + check_unaligned_access_emulated(NULL); /* * If unaligned_ctl is already set, this means that we detected that all @@ -654,9 +662,10 @@ void check_unaligned_access_emulated(struct work_struct *work __always_unused) */ if (unlikely(unaligned_ctl && (*mas_ptr != RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED))) { pr_crit("CPU misaligned accesses non homogeneous (expected all emulated)\n"); - while (true) - cpu_relax(); + return -EINVAL; } + + return 0; } bool check_unaligned_access_emulated_all_cpus(void) @@ -688,4 +697,66 @@ bool check_unaligned_access_emulated_all_cpus(void) { return false; } +static int cpu_online_check_unaligned_access_emulated(unsigned int cpu) +{ + return 0; +} #endif + +#ifdef CONFIG_RISCV_SBI + +static bool misaligned_traps_delegated; + +static int cpu_online_sbi_unaligned_setup(unsigned int cpu) +{ + if (sbi_fwft_set(SBI_FWFT_MISALIGNED_EXC_DELEG, 1, 0) && + misaligned_traps_delegated) { + pr_crit("Misaligned trap delegation non homogeneous (expected delegated)"); + return -EINVAL; + } + + return 0; +} + +static void unaligned_sbi_request_delegation(void) +{ + int ret; + + ret = sbi_fwft_local_set(SBI_FWFT_MISALIGNED_EXC_DELEG, 1, 0); + if (ret) + return; + + misaligned_traps_delegated = true; + pr_info("SBI misaligned access exception delegation ok\n"); + /* + * Note that we don't have to take any specific action here, if + * the delegation is successful, then + * check_unaligned_access_emulated() will verify that indeed the + * platform traps on misaligned accesses. + */ +} + +void unaligned_access_init(void) +{ + if (sbi_probe_extension(SBI_EXT_FWFT) > 0) + unaligned_sbi_request_delegation(); +} +#else +void unaligned_access_init(void) {} + +static int cpu_online_sbi_unaligned_setup(unsigned int cpu __always_unused) +{ + return 0; +} +#endif + +int cpu_online_unaligned_access_init(unsigned int cpu) +{ + int ret; + + ret = cpu_online_sbi_unaligned_setup(cpu); + if (ret) + return ret; + + return cpu_online_check_unaligned_access_emulated(cpu); +} diff --git a/arch/riscv/kernel/unaligned_access_speed.c b/arch/riscv/kernel/unaligned_access_speed.c index 91f189cf1611..2f3aba073297 100644 --- a/arch/riscv/kernel/unaligned_access_speed.c +++ b/arch/riscv/kernel/unaligned_access_speed.c @@ -188,13 +188,20 @@ arch_initcall_sync(lock_and_set_unaligned_access_static_branch); static int riscv_online_cpu(unsigned int cpu) { + int ret; static struct page *buf; /* We are already set since the last check */ if (per_cpu(misaligned_access_speed, cpu) != RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN) goto exit; - check_unaligned_access_emulated(NULL); + ret = cpu_online_unaligned_access_init(cpu); + if (ret) + return ret; + + if (per_cpu(misaligned_access_speed, cpu) == RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED) + goto exit; + buf = alloc_pages(GFP_KERNEL, MISALIGNED_BUFFER_ORDER); if (!buf) { pr_warn("Allocation failure, not measuring misaligned performance\n"); @@ -403,6 +410,8 @@ static int check_unaligned_access_all_cpus(void) { bool all_cpus_emulated, all_cpus_vec_unsupported; + unaligned_access_init(); + all_cpus_emulated = check_unaligned_access_emulated_all_cpus(); all_cpus_vec_unsupported = check_vector_unaligned_access_emulated_all_cpus();