From patchwork Fri Mar 21 17:22:40 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 14025874 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2BC1CC36000 for ; Fri, 21 Mar 2025 18:34:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=4zWqBwQ2wUuifS3SEIK++K551aSObyAsAZZ1oudlfIs=; b=z2/ClEp3iXPVZh Kw640LzcRytguhv+76WnsNZQCmiImc7Tl2t8Moz28ExxtWn/JUC5UV8TJw+JZ6v6mgdFBbEdhp1fd 9ninIcWVZXZkym88NMvxZFpi7SLmlM6xQymmGNjWxxj8Z6JjFe72b04itteLtHJft+wiavee0U/bo Mm28VBSww/1ccVlQ02eD1Zk46QynD7ciIwCFNmooZBMA5IqJu/EpZ0AsKxoG8SFM5DfCth0eRxzif s+8dwmPfu77OCpLq/CRwj5OY+BvDrEsVAy3v+XNcx+K99Ev+BsuTCGDv5ZtEE7CfNIU43Njef27Zg dsHD9CjImc8Yi4U8NXyg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tvhCN-0000000Fs1W-48gR; Fri, 21 Mar 2025 18:34:27 +0000 Received: from sea.source.kernel.org ([2600:3c0a:e001:78e:0:1991:8:25]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tvg5q-0000000Fgjb-2YYM for linux-riscv@lists.infradead.org; Fri, 21 Mar 2025 17:23:39 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sea.source.kernel.org (Postfix) with ESMTP id D3DF244106; Fri, 21 Mar 2025 17:23:37 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id D7035C4CEE3; Fri, 21 Mar 2025 17:23:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1742577818; bh=f9XLsCJlmlDSiEFANz3UPnWGwYytvFNhw2FHQbcHCQA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=fcNl2pnJFseTpGGz8bNi+X09lJGJ018ul/XCE0i9VPfT+BJkow0gI/DnF8Cp3iZhE c5Mq+uqRELR26G6UPozuYiCMGL+GMkrPS8qH8Uv4w+nc8K0FfrfTeX85r8nrmdoVln pRg59vZqqSbGjhuBcO+tL7yeugwlS4meAcAXLSNgEuyWQ/Mag3iCCDs27MYrVFt74I GF4Wn716zkHFPiNrvCC/9MrmCqI3mEhfIPpFpBIMsWxe7p8d9AoJ1xC/KvRvq0Mdsm Z4xXPNCOcxV3zcug2rTXKvHyKBSr+H4sKI4VJJVu75hR01AjQy2ubSyWs3HhEkpFoC ejYFl/WGW8LAg== From: Conor Dooley To: Stephen Boyd Cc: conor@kernel.org, Conor Dooley , Daire McNamara , pierre-henry.moussay@microchip.com, valentina.fernandezalanis@microchip.com, Michael Turquette , Rob Herring , Krzysztof Kozlowski , Jassi Brar , Lee Jones , Paul Walmsley , Palmer Dabbelt , Philipp Zabel , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH v2 7/9] riscv: dts: microchip: convert clock and reset to use syscon Date: Fri, 21 Mar 2025 17:22:40 +0000 Message-ID: <20250321-ferocious-projector-c22da63afe21@spud> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250321-cuddly-hazily-d0ab1e1747b5@spud> References: <20250321-cuddly-hazily-d0ab1e1747b5@spud> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2216; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=PM6cFJ1IerUUu+VkUFTnmY9mCANBqD5NBbof7moNREM=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDOl3F0RxeG3fdmDV7h1xD54pqrBb62+MMS1gqzhqyf61Q UZD7/W6jlIWBjEOBlkxRZbE230tUuv/uOxw7nkLM4eVCWQIAxenAExklRUjw72/Ru42Spwftcqr I93mSwoG2oeYPqpZNOf1wXkcPwpblBn+eyU87lnw4Ifaj8eHdm+1/lWvoj55tonwM+NJ+R5NWxY YMwIA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250321_102338_688764_0F5D528F X-CRM114-Status: GOOD ( 10.71 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Conor Dooley The "subblock" clocks and reset registers on PolarFire SoC are located in the mss-top-sysreg region, alongside pinctrl and interrupt control functionality. Re-write the devicetree to describe the sys explicitly, as its own node, rather than as a region of the clock node. Correspondingly, the phandles to the reset controller must be updated to the new provider. The drivers will continue to support the old way of doing things. Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/mpfs.dtsi | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi index f9d6bf08e717..5c2963e269b8 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -251,11 +251,9 @@ pdma: dma-controller@3000000 { #dma-cells = <1>; }; - clkcfg: clkcfg@20002000 { - compatible = "microchip,mpfs-clkcfg"; - reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>; - clocks = <&refclk>; - #clock-cells = <1>; + mss_top_sysreg: syscon@20002000 { + compatible = "microchip,mpfs-mss-top-sysreg", "syscon", "simple-mfd"; + reg = <0x0 0x20002000 0x0 0x1000>; #reset-cells = <1>; }; @@ -452,7 +450,7 @@ mac0: ethernet@20110000 { local-mac-address = [00 00 00 00 00 00]; clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>; clock-names = "pclk", "hclk"; - resets = <&clkcfg CLK_MAC0>; + resets = <&mss_top_sysreg CLK_MAC0>; status = "disabled"; }; @@ -466,7 +464,7 @@ mac1: ethernet@20112000 { local-mac-address = [00 00 00 00 00 00]; clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>; clock-names = "pclk", "hclk"; - resets = <&clkcfg CLK_MAC1>; + resets = <&mss_top_sysreg CLK_MAC1>; status = "disabled"; }; @@ -550,5 +548,12 @@ syscontroller_qspi: spi@37020100 { clocks = <&scbclk>; status = "disabled"; }; + + clkcfg: clkcfg@3e001000 { + compatible = "microchip,mpfs-clkcfg"; + reg = <0x0 0x3e001000 0x0 0x1000>; + clocks = <&refclk>; + #clock-cells = <1>; + }; }; };