From patchwork Fri Mar 21 17:22:38 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 14025830 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6B780C36000 for ; Fri, 21 Mar 2025 17:23:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=OlphIQ8CVYYEbel2B7sz044BJeGVor2mStPQdkzGyfk=; b=JB3He1KaINdtJI gAMxViEYqR1FiMH82mvuqusZ6jMm4OParLZtrgycQCk3uLLVnwQ1iXVYuJOzugaOMe89bfuPzcKMC wuqWx1g696017+lWMkTfewBMRgqNmO7uouZegBmNqXEu86LJ578BX/qs+HQ3TNcyFcebdDXyuAqic VA4I153/HVBw4pAl2Ex1Bh7PjtE4wxKn/LQfmGca2OTOoeZuVxmNhpzhP2YDaw3N1EDBNmsPEPHbS 3YPCghgjYwpgBeIpGcD0EbjIVERPy4ZFeb1W/Wy4DHohvYXbC2X2OJOTcNrvK1VthXenKKPhT09y8 T57Q87w/5rbWAbvu/Lvg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tvg5l-0000000Fget-1osS; Fri, 21 Mar 2025 17:23:33 +0000 Received: from sea.source.kernel.org ([172.234.252.31]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tvg5j-0000000FgdD-1Cea for linux-riscv@lists.infradead.org; Fri, 21 Mar 2025 17:23:32 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sea.source.kernel.org (Postfix) with ESMTP id 73C2943BA2; Fri, 21 Mar 2025 17:23:30 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 72855C4CEE8; Fri, 21 Mar 2025 17:23:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1742577810; bh=NRPZVMg8q8Glkkek+MZ6GcEzInHhK6SX1BhDs6BGtW4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mo0eTwd46VQIln6hxjk3OQXTODpg3IEBL3QgxORx7opDBGbPqm3zC6Tb3yZAnFUg/ ZfpHYuSCjNlR/W/PK9ES7Ynnp/fwBiD876cWYfGvFV8z+wz0pSjQLZrmskSN8zl8nu SGkrln0yZmXOtbMigQ1XaPHtnJ9lu3DMf5iOsnilfEIupaiALC7p6GfmwHuCiY4/VV jOrn/icFy1wII4u601qNyFYII4LpKDB0B6jQvmMEYxyV8Q6pPWYB5tAIZDn4nWAuq+ xNvTtgEyb5E8w7Bjx3I1sMSwH1U8lM/HQr7VBcq51yMidT0Lt+XasT+1z5cbkHc5Wr 7FNOFHo/EvjpQ== From: Conor Dooley To: Stephen Boyd Cc: conor@kernel.org, Conor Dooley , Daire McNamara , pierre-henry.moussay@microchip.com, valentina.fernandezalanis@microchip.com, Michael Turquette , Rob Herring , Krzysztof Kozlowski , Jassi Brar , Lee Jones , Paul Walmsley , Palmer Dabbelt , Philipp Zabel , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH v2 5/9] dt-bindings: clk: microchip: mpfs: remove first reg region Date: Fri, 21 Mar 2025 17:22:38 +0000 Message-ID: <20250321-majesty-overhung-1441f3858efc@spud> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250321-cuddly-hazily-d0ab1e1747b5@spud> References: <20250321-cuddly-hazily-d0ab1e1747b5@spud> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3159; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=PXlK/3bLOMNEyxgWeBhvy5NgnPZBRf51ELypfcFIriA=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDOl3F0TN8Nev1tRQ3O5wNHDiGTafNYdszRYKFQkzbSqa7 86i/bamo5SFQYyDQVZMkSXxdl+L1Po/Ljuce97CzGFlAhnCwMUpABMxnsbIcGvGSY3l/1sn205d XNi/J3Vbt0qJefYOuV1tSrn/ZsT/NmH4pxWYLs7NPm9FRlOFnPfyV3Ilm5SSbM9Lf5/lfO+F1oG 9TAA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250321_102331_370536_BE9AF882 X-CRM114-Status: GOOD ( 11.47 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Conor Dooley The first reg region in this binding is not exclusively for clocks, as evidenced by the dual role of this device as a reset controller at present. The first region is however better described by a simple-mfd syscon, but this would have require a significant re-write of the devicetree for the platform, so the easy way out was chosen when reset support was first introduced. The region doesn't just contain clock and reset registers, it also contains pinctrl and interrupt controller functionality, so drop the region from the clock binding so that it can be described instead by a simple-mfd syscon rather than propagate this incorrect description of the hardware to the new pic64gx SoC. Acked-by: Rob Herring (Arm) Signed-off-by: Conor Dooley --- .../bindings/clock/microchip,mpfs-clkcfg.yaml | 36 +++++++++++-------- 1 file changed, 22 insertions(+), 14 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml b/Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml index e4e1c31267d2..ee4f31596d97 100644 --- a/Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml +++ b/Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml @@ -22,16 +22,23 @@ properties: const: microchip,mpfs-clkcfg reg: - items: - - description: | - clock config registers: - These registers contain enable, reset & divider tables for the, cpu, - axi, ahb and rtc/mtimer reference clocks as well as enable and reset - for the peripheral clocks. - - description: | - mss pll dri registers: - Block of registers responsible for dynamic reconfiguration of the mss - pll + oneOf: + - items: + - description: | + clock config registers: + These registers contain enable, reset & divider tables for the, cpu, + axi, ahb and rtc/mtimer reference clocks as well as enable and reset + for the peripheral clocks. + - description: | + mss pll dri registers: + Block of registers responsible for dynamic reconfiguration of the mss + pll + deprecated: true + - items: + - description: | + mss pll dri registers: + Block of registers responsible for dynamic reconfiguration of the mss + pll clocks: maxItems: 1 @@ -69,11 +76,12 @@ examples: - | #include soc { - #address-cells = <2>; - #size-cells = <2>; - clkcfg: clock-controller@20002000 { + #address-cells = <1>; + #size-cells = <1>; + + clkcfg: clock-controller@3E001000 { compatible = "microchip,mpfs-clkcfg"; - reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>; + reg = <0x3E001000 0x1000>; clocks = <&ref>; #clock-cells = <1>; };