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Tue, 01 Apr 2025 10:24:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=4d2.org; s=mail; t=1743528297; bh=8c6COWP7Dw3rM2JKdudVcfXRIkxcSQg0Ocq+QX4CSfI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cmCWb2WvS0S0sSOMt0p6Fk0Ek5jNVTrnK4TqJoWo/WpJbwcXYq7/lT8goDlll+cKv vQMYO3ORaxY+M1l1ehdufm9BW5jyg1jeHI9TrvWx9B2a56PZkx0s/ttwwjSoKPvBk3 HjMRsqoq2XSY9oCbvBcKZn8iOcr7h6frrsDRr/FxhC/xhVHNGvrvg2wQMPWrtL6kwd K+Q7ZkTHaH0Hb7umMMgWkaubgic53iqX9HowrxrwLtoPeed7FPFfwXbiQ7ILCsZl9N /TbEdXNQkYAUizzha5LM/irUgG02DKYP7GMWX3KYiW/sb+I8Zj32h4tFDactjRyqKS XSbkjbtMjJJjA== From: Haylen Chu To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Haylen Chu , Yixun Lan , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti Cc: linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, spacemit@lists.linux.dev, Inochi Amaoto , Chen Wang , Jisheng Zhang , Meng Zhang , Haylen Chu , Krzysztof Kozlowski Subject: [PATCH v6 2/6] dt-bindings: clock: spacemit: Add spacemit,k1-pll Date: Tue, 1 Apr 2025 17:24:30 +0000 Message-ID: <20250401172434.6774-3-heylenay@4d2.org> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250401172434.6774-1-heylenay@4d2.org> References: <20250401172434.6774-1-heylenay@4d2.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250401_102459_521955_93358C2A X-CRM114-Status: GOOD ( 13.96 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add definition for the PLL found on SpacemiT K1 SoC, which takes the external 24MHz oscillator as input and generates clocks in various frequencies for the system. Signed-off-by: Haylen Chu Reviewed-by: Krzysztof Kozlowski --- .../bindings/clock/spacemit,k1-pll.yaml | 50 +++++++++++++++++++ .../dt-bindings/clock/spacemit,k1-syscon.h | 37 ++++++++++++++ 2 files changed, 87 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/spacemit,k1-pll.yaml diff --git a/Documentation/devicetree/bindings/clock/spacemit,k1-pll.yaml b/Documentation/devicetree/bindings/clock/spacemit,k1-pll.yaml new file mode 100644 index 000000000000..06bafd68c00a --- /dev/null +++ b/Documentation/devicetree/bindings/clock/spacemit,k1-pll.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/spacemit,k1-pll.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SpacemiT K1 PLL + +maintainers: + - Haylen Chu + +properties: + compatible: + const: spacemit,k1-pll + + reg: + maxItems: 1 + + clocks: + description: External 24MHz oscillator + + spacemit,mpmu: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the "Main PMU (MPMU)" syscon. It is used to check PLL + lock status. + + "#clock-cells": + const: 1 + description: + See for valid indices. + +required: + - compatible + - reg + - clocks + - spacemit,mpmu + - "#clock-cells" + +additionalProperties: false + +examples: + - | + clock-controller@d4090000 { + compatible = "spacemit,k1-pll"; + reg = <0xd4090000 0x1000>; + clocks = <&vctcxo_24m>; + spacemit,mpmu = <&sysctl_mpmu>; + #clock-cells = <1>; + }; diff --git a/include/dt-bindings/clock/spacemit,k1-syscon.h b/include/dt-bindings/clock/spacemit,k1-syscon.h index 61c8d7360cf8..efe29c976a01 100644 --- a/include/dt-bindings/clock/spacemit,k1-syscon.h +++ b/include/dt-bindings/clock/spacemit,k1-syscon.h @@ -6,6 +6,43 @@ #ifndef _DT_BINDINGS_SPACEMIT_CCU_H_ #define _DT_BINDINGS_SPACEMIT_CCU_H_ +/* APBS (PLL) clocks */ +#define CLK_PLL1 0 +#define CLK_PLL2 1 +#define CLK_PLL3 2 +#define CLK_PLL1_D2 3 +#define CLK_PLL1_D3 4 +#define CLK_PLL1_D4 5 +#define CLK_PLL1_D5 6 +#define CLK_PLL1_D6 7 +#define CLK_PLL1_D7 8 +#define CLK_PLL1_D8 9 +#define CLK_PLL1_D11 10 +#define CLK_PLL1_D13 11 +#define CLK_PLL1_D23 12 +#define CLK_PLL1_D64 13 +#define CLK_PLL1_D10_AUD 14 +#define CLK_PLL1_D100_AUD 15 +#define CLK_PLL2_D1 16 +#define CLK_PLL2_D2 17 +#define CLK_PLL2_D3 18 +#define CLK_PLL2_D4 19 +#define CLK_PLL2_D5 20 +#define CLK_PLL2_D6 21 +#define CLK_PLL2_D7 22 +#define CLK_PLL2_D8 23 +#define CLK_PLL3_D1 24 +#define CLK_PLL3_D2 25 +#define CLK_PLL3_D3 26 +#define CLK_PLL3_D4 27 +#define CLK_PLL3_D5 28 +#define CLK_PLL3_D6 29 +#define CLK_PLL3_D7 30 +#define CLK_PLL3_D8 31 +#define CLK_PLL3_80 32 +#define CLK_PLL3_40 33 +#define CLK_PLL3_20 34 + /* MPMU clocks */ #define CLK_PLL1_307P2 0 #define CLK_PLL1_76P8 1