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Tue, 01 Apr 2025 10:25:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=4d2.org; s=mail; t=1743528307; bh=UEi+X0opYSOBwIaTJ9L7fBGwSzYPjuB8SAkUHzqDMpY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=I5V0Kwfu19eg10Kz2m6Tghi4JitDOo3WUhjJ76ob2uAqQcY3KUQgURnUrzSo5HaKC ultpXw+gQZYvVDKEQ6yKHJUBb3Vby3JE+WikS1NgA847n9BNrLcFQaSwcJoO8CfyFQ 9j2XrOx/Eq564WeSIocrqJuazxlqCBlUm0wdRJaH+SURyaK2WIfIyU/JrLiABbTYl6 +x27Q8IjeQG0y1Hwl9ZslB1uz06TzY+EjCUZMiE/c54o4oz+OpJsqCfNsBuS7S9gSQ g221j1EblU7E6RgnzEnh4grINQrUk65xYDfiDRA40i+b1ils155ocIaHRrMgx+Qc5e bCWO7iHjUtw/g== From: Haylen Chu To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Haylen Chu , Yixun Lan , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti Cc: linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, spacemit@lists.linux.dev, Inochi Amaoto , Chen Wang , Jisheng Zhang , Meng Zhang , Haylen Chu Subject: [PATCH v6 4/6] clk: spacemit: k1: Add TWSI8 bus and function clocks Date: Tue, 1 Apr 2025 17:24:32 +0000 Message-ID: <20250401172434.6774-5-heylenay@4d2.org> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250401172434.6774-1-heylenay@4d2.org> References: <20250401172434.6774-1-heylenay@4d2.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250401_102509_839653_27E59CC0 X-CRM114-Status: GOOD ( 11.76 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The control register for TWSI8 clocks, APBC_TWSI8_CLK_RST, contains mux selection bits, reset assertion bit and enable bits for function and bus clocks. It has a quirk that reading always results in zero. As a workaround, let's hardcode the mux value as zero to select pll1_d78_31p5 as parent and treat twsi8_clk as a gate, whose enable mask is combined from the real bus and function clocks to avoid the write-only register being shared between two clk_hws, in which case updates of one clk_hw zero the other's bits. With a 1:1 factor serving as placeholder for the bus clock, the I2C-8 controller could be brought up, which is essential for boards attaching power-management chips to it. Signed-off-by: Haylen Chu --- drivers/clk/spacemit/ccu-k1.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/clk/spacemit/ccu-k1.c b/drivers/clk/spacemit/ccu-k1.c index cd95c4f9c127..5804c2f85407 100644 --- a/drivers/clk/spacemit/ccu-k1.c +++ b/drivers/clk/spacemit/ccu-k1.c @@ -397,6 +397,8 @@ CCU_MUX_GATE_DEFINE(twsi6_clk, twsi_parents, APBC_TWSI6_CLK_RST, 4, 3, BIT(1), 0); CCU_MUX_GATE_DEFINE(twsi7_clk, twsi_parents, APBC_TWSI7_CLK_RST, 4, 3, BIT(1), 0); +CCU_GATE_DEFINE(twsi8_clk, CCU_PARENT_HW(pll1_d78_31p5), APBC_TWSI8_CLK_RST, + BIT(1) | BIT(0), 0); static const struct clk_parent_data timer_parents[] = { CCU_PARENT_HW(pll1_d192_12p8), @@ -528,6 +530,7 @@ CCU_GATE_DEFINE(twsi6_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI6_CLK_RST, BIT(0), 0); CCU_GATE_DEFINE(twsi7_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI7_CLK_RST, BIT(0), 0); +CCU_FACTOR_DEFINE(twsi8_bus_clk, CCU_PARENT_HW(apb_clk), 1, 1); CCU_GATE_DEFINE(timers1_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TIMERS1_CLK_RST, BIT(0), 0); @@ -1059,6 +1062,7 @@ static struct clk_hw *k1_ccu_apbc_hws[] = { [CLK_TWSI5] = &twsi5_clk.common.hw, [CLK_TWSI6] = &twsi6_clk.common.hw, [CLK_TWSI7] = &twsi7_clk.common.hw, + [CLK_TWSI8] = &twsi8_clk.common.hw, [CLK_TIMERS1] = &timers1_clk.common.hw, [CLK_TIMERS2] = &timers2_clk.common.hw, [CLK_AIB] = &aib_clk.common.hw, @@ -1110,6 +1114,7 @@ static struct clk_hw *k1_ccu_apbc_hws[] = { [CLK_TWSI5_BUS] = &twsi5_bus_clk.common.hw, [CLK_TWSI6_BUS] = &twsi6_bus_clk.common.hw, [CLK_TWSI7_BUS] = &twsi7_bus_clk.common.hw, + [CLK_TWSI8_BUS] = &twsi8_bus_clk.common.hw, [CLK_TIMERS1_BUS] = &timers1_bus_clk.common.hw, [CLK_TIMERS2_BUS] = &timers2_bus_clk.common.hw, [CLK_AIB_BUS] = &aib_bus_clk.common.hw,