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AJvYcCXIvmArkh6FkoBPl9qIHCNfTigXkE71agrHu4FSXk8VVBx+r2b7jkzf+eZzki31sWcFY4PZI2WGxXrLMg==@lists.infradead.org X-Gm-Message-State: AOJu0Yzwu6Xi6E3TynPaiooPCELu+D3N/u/VUT//KGOt7xnLuPnGV6a/ 93LdF+bMk4eYdpvrZwtDXTKS55Bc9+SylZflom/r8IJntm0eC6vj X-Google-Smtp-Source: AGHT+IHh+BOXyYZhMqca+Gp9Z6ku4LYrEw/r5Gi1ZCkkbWzyDTxWRs1YU+MyFQM7QKIs4EIKe1PY/w== X-Received: by 2002:a05:6830:d02:b0:70f:331e:90f6 with SMTP id 46e09a7af769-70f5c466677mr33305848a34.23.1725538249874; Thu, 05 Sep 2024 05:10:49 -0700 (PDT) Received: from localhost.localdomain ([122.8.183.87]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-70f671cf763sm3248566a34.80.2024.09.05.05.10.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Sep 2024 05:10:49 -0700 (PDT) From: Chen Wang To: ukleinek@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, unicorn_wang@outlook.com, inochiama@outlook.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org, linux-riscv@lists.infradead.org, chao.wei@sophgo.com, haijiao.liu@sophgo.com, xiaoguang.xing@sophgo.com, chunzhi.lin@sophgo.com Subject: [PATCH 2/2] pwm: sophgo: add driver for Sophgo SG2042 PWM Date: Thu, 5 Sep 2024 20:10:42 +0800 Message-Id: <3985690b29340982a45314bdcc914c554621e909.1725536870.git.unicorn_wang@outlook.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240905_051051_375846_6D664768 X-CRM114-Status: GOOD ( 23.06 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Chen Wang Add a PWM driver for PWM controller in Sophgo SG2042 SoC. Signed-off-by: Chen Wang --- drivers/pwm/Kconfig | 9 ++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-sophgo-sg2042.c | 148 ++++++++++++++++++++++++++++++++ 3 files changed, 158 insertions(+) create mode 100644 drivers/pwm/pwm-sophgo-sg2042.c diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 3e53838990f5..6287d63a84fd 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -577,6 +577,15 @@ config PWM_SL28CPLD To compile this driver as a module, choose M here: the module will be called pwm-sl28cpld. +config PWM_SOPHGO_SG2042 + tristate "Sophgo SG2042 PWM support" + depends on ARCH_SOPHGO || COMPILE_TEST + help + PWM driver for Sophgo SG2042 PWM controller. + + To compile this driver as a module, choose M here: the module + will be called pwm_sophgo_sg2042. + config PWM_SPEAR tristate "STMicroelectronics SPEAr PWM support" depends on PLAT_SPEAR || COMPILE_TEST diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 0be4f3e6dd43..ef2555e83183 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -52,6 +52,7 @@ obj-$(CONFIG_PWM_RZ_MTU3) += pwm-rz-mtu3.o obj-$(CONFIG_PWM_SAMSUNG) += pwm-samsung.o obj-$(CONFIG_PWM_SIFIVE) += pwm-sifive.o obj-$(CONFIG_PWM_SL28CPLD) += pwm-sl28cpld.o +obj-$(CONFIG_PWM_SOPHGO_SG2042) += pwm-sophgo-sg2042.o obj-$(CONFIG_PWM_SPEAR) += pwm-spear.o obj-$(CONFIG_PWM_SPRD) += pwm-sprd.o obj-$(CONFIG_PWM_STI) += pwm-sti.o diff --git a/drivers/pwm/pwm-sophgo-sg2042.c b/drivers/pwm/pwm-sophgo-sg2042.c new file mode 100644 index 000000000000..cf11ad54b4de --- /dev/null +++ b/drivers/pwm/pwm-sophgo-sg2042.c @@ -0,0 +1,148 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Sophgo SG2042 PWM Controller Driver + * + * Copyright (C) 2024 Sophgo Technology Inc. + * Copyright (C) 2024 Chen Wang + */ + +#include +#include +#include +#include +#include +#include + +#include + +/* + * Offset RegisterName + * 0x0000 HLPERIOD0 + * 0x0004 PERIOD0 + * 0x0008 HLPERIOD1 + * 0x000C PERIOD1 + * 0x0010 HLPERIOD2 + * 0x0014 PERIOD2 + * 0x0018 HLPERIOD3 + * 0x001C PERIOD3 + * Four groups and every group is composed of HLPERIOD & PERIOD + */ +#define REG_HLPERIOD 0x0 +#define REG_PERIOD 0x4 + +#define REG_GROUP 0x8 + +#define SG2042_PWM_CHANNELNUM 4 + +/** + * struct sg2042_pwm_chip - private data of PWM chip + * @base: base address of mapped PWM registers + * @base_clk: base clock used to drive the pwm controller + */ +struct sg2042_pwm_chip { + void __iomem *base; + struct clk *base_clk; +}; + +static inline +struct sg2042_pwm_chip *to_sg2042_pwm_chip(struct pwm_chip *chip) +{ + return pwmchip_get_drvdata(chip); +} + +static void pwm_sg2042_config(void __iomem *base, unsigned int channo, u32 period, u32 hlperiod) +{ + writel(period, base + REG_GROUP * channo + REG_PERIOD); + writel(hlperiod, base + REG_GROUP * channo + REG_HLPERIOD); +} + +static int pwm_sg2042_apply(struct pwm_chip *chip, struct pwm_device *pwm, + const struct pwm_state *state) +{ + struct sg2042_pwm_chip *sg2042_pwm = to_sg2042_pwm_chip(chip); + u32 hlperiod; + u32 period; + u64 f_clk; + u64 p; + + if (!state->enabled) { + pwm_sg2042_config(sg2042_pwm->base, pwm->hwpwm, 0, 0); + return 0; + } + + /* + * Period of High level (duty_cycle) = HLPERIOD x Period_clk + * Period of One Cycle (period) = PERIOD x Period_clk + */ + f_clk = clk_get_rate(sg2042_pwm->base_clk); + + p = f_clk * state->period; + do_div(p, NSEC_PER_SEC); + period = (u32)p; + + p = f_clk * state->duty_cycle; + do_div(p, NSEC_PER_SEC); + hlperiod = (u32)p; + + dev_dbg(pwmchip_parent(chip), "chan[%d]: period=%u, hlperiod=%u\n", + pwm->hwpwm, period, hlperiod); + + pwm_sg2042_config(sg2042_pwm->base, pwm->hwpwm, period, hlperiod); + + return 0; +} + +static const struct pwm_ops pwm_sg2042_ops = { + .apply = pwm_sg2042_apply, +}; + +static const struct of_device_id sg2042_pwm_match[] = { + { .compatible = "sophgo,sg2042-pwm" }, + { }, +}; +MODULE_DEVICE_TABLE(of, sg2042_pwm_match); + +static int pwm_sg2042_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct sg2042_pwm_chip *sg2042_pwm; + struct pwm_chip *chip; + int ret; + + chip = devm_pwmchip_alloc(&pdev->dev, SG2042_PWM_CHANNELNUM, sizeof(*sg2042_pwm)); + if (IS_ERR(chip)) + return PTR_ERR(chip); + sg2042_pwm = to_sg2042_pwm_chip(chip); + + chip->ops = &pwm_sg2042_ops; + + sg2042_pwm->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(sg2042_pwm->base)) + return PTR_ERR(sg2042_pwm->base); + + sg2042_pwm->base_clk = devm_clk_get_enabled(&pdev->dev, "apb"); + if (IS_ERR(sg2042_pwm->base_clk)) + return dev_err_probe(dev, PTR_ERR(sg2042_pwm->base_clk), + "failed to get base clk\n"); + + ret = devm_pwmchip_add(&pdev->dev, chip); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to register PWM chip\n"); + + platform_set_drvdata(pdev, chip); + + return 0; +} + +static struct platform_driver pwm_sg2042_driver = { + .driver = { + .name = "sg2042-pwm", + .of_match_table = of_match_ptr(sg2042_pwm_match), + }, + .probe = pwm_sg2042_probe, +}; +module_platform_driver(pwm_sg2042_driver); + +MODULE_AUTHOR("Chen Wang"); +MODULE_DESCRIPTION("Sophgo SG2042 PWM driver"); +MODULE_LICENSE("GPL");