From patchwork Sat Jun 15 05:27:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Jeznach X-Patchwork-Id: 13699231 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E79E0C2BA15 for ; Sat, 15 Jun 2024 05:28:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=KtnOC4J/vcwmw2WfLcoOV5kMBAbZfbWlasRnwSn9zf4=; b=dLkiF7GIlSvaGT vuREByCyerMfbbddBmwbC/5xlmFtki8P9+mE2pUT6TS6Q7Enzp/sTAGp5BZ7idoIyN5aFpWI56b3B hcUcilJmY2mHGzEeWdZYrYXgBRtWLYVywokwAjoaa+51vQWkty8f10MoE23auR02y/UxDizZH3VCr 2u4Fyyp+j/1aG24jqCE0EikZ7vj2mcTNCO37qHACqqUdueGec3jfh/QIz+/2JyVMG2wdambG8xXOt PiuM0cIdDrLFLJBCPlfEb7ooTOczGq1N/BIHpB88DTzp6IBodJJwmoZa84RlXFegtfKxMKWprmBvP SiJcdtsjqqsmOs9uMyUQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sILxF-00000004iXi-3DfE; Sat, 15 Jun 2024 05:27:57 +0000 Received: from mail-pf1-x431.google.com ([2607:f8b0:4864:20::431]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sILxB-00000004iVa-04LA for linux-riscv@lists.infradead.org; Sat, 15 Jun 2024 05:27:55 +0000 Received: by mail-pf1-x431.google.com with SMTP id d2e1a72fcca58-7024d571d8eso2231096b3a.0 for ; Fri, 14 Jun 2024 22:27:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1718429270; x=1719034070; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hX4rXy+acmv+ohoMY8KkeM2ChnDNLgiOcjEcwsmP8c0=; b=uqT2wRQ2x+dLR5MT0OW4pnbmkeZ0vyg3wRcPAdputKVmcrcGtTmN5QN4MbksTyTR4n ghPMDizDOylVhTyLmN7gAWP+WpHW9SttCQX37wCXLrRyPHNnrjrGHR3YRyTvVxtPVuFa YDM620ExAK+8TkK5O9XYToFPdE8ONpf2ejE8KbaXBRIBQORLZkeOu5bpAZyNF7MiPNP2 QwAKFumeXDw71MD3PaTgn7SC9e9wd2nNxfgn1b6AZxj4KfBfjtxZDQnet2vf0mOG4u2m BqjFOlw03kJmDQqiS+SITrZUgKhSY2Q7FhCxZO3zvzyztZuJnwITn2ct4RoxVbS6vn1F Cfog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1718429270; x=1719034070; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hX4rXy+acmv+ohoMY8KkeM2ChnDNLgiOcjEcwsmP8c0=; b=DRx235I8I7mR5NPEnIzdJksMgTvysrZ2nIbPrNyLHET4TqhX2kmYAyrIuWFx5V0uXC 3+3N8b7EWNOFDYhknhrOa1rHAww6D5MIH9C1wBXy75PXjw4P1PPTqB0Yw8X1OtJ7XNcj kjpdHJ2H2MOPzFk9wMeMlT+4hRZ75UiL4BdGGh/9X1djf5pc75CRcAdljrZqMGG/4hXR 82F52o9dciJCsYUgnQEL170c5QIsXhl3V4o4dhhq6QF7VUBLRA9ng3aRmYAM0sGX+ys3 3Bb0cbkVmIZuBWcDEp+VW/36UsHUicgPYG4GYJF9L5p3MIR3tCRsBHXlzc+miGrBSSzO RfDg== X-Forwarded-Encrypted: i=1; AJvYcCUohW6OADb/OqZpLSBWmjK+0eFPL3dGRLP0Ph39R+zfniJ+RkyTKKqQv36cLfFCOOrAL+UvjOrq42wo4DYhDly2BUmCPbXb595fRpfWFO63 X-Gm-Message-State: AOJu0Yw6BYqo5+kfwy7CZfrtl5Z9oDkDgp+HVyklE1jN06WTe1dudLAn 5HzvPcd0DRsOJmDzW4p5MvJybl6+BgIp5ludIZPNLkga6exW+jmU0cSemgwGIO4= X-Google-Smtp-Source: AGHT+IHHB00LSgBpCRZzG8htXgrCrDS+dLyQHnBhTgRkH7wA58M/K+DxEN+n2UkQ79mL1S1cgQKB6Q== X-Received: by 2002:a05:6a00:114e:b0:705:dd44:ae77 with SMTP id d2e1a72fcca58-705dd44b04emr4715791b3a.3.1718429269869; Fri, 14 Jun 2024 22:27:49 -0700 (PDT) Received: from tjeznach.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-705ccb6b99bsm4081578b3a.143.2024.06.14.22.27.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Jun 2024 22:27:48 -0700 (PDT) From: Tomasz Jeznach To: Joerg Roedel , Will Deacon , Robin Murphy , Paul Walmsley Subject: [PATCH v8 1/7] dt-bindings: iommu: riscv: Add bindings for RISC-V IOMMU Date: Fri, 14 Jun 2024 22:27:31 -0700 Message-Id: <90f6ecaa9afc6fe4edf005f4d19175446f7afd11.1718388908.git.tjeznach@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240614_222753_084751_91C75D5C X-CRM114-Status: GOOD ( 17.36 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Anup Patel , devicetree@vger.kernel.org, Conor Dooley , Albert Ou , Tomasz Jeznach , linux@rivosinc.com, Rob Herring , Conor Dooley , linux-kernel@vger.kernel.org, Rob Herring , Sebastien Boeuf , iommu@lists.linux.dev, Palmer Dabbelt , Nick Kossifidis , Krzysztof Kozlowski , linux-riscv@lists.infradead.org Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add bindings for the RISC-V IOMMU device drivers. Co-developed-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Conor Dooley Reviewed-by: Rob Herring (Arm) Signed-off-by: Tomasz Jeznach --- .../bindings/iommu/riscv,iommu.yaml | 147 ++++++++++++++++++ MAINTAINERS | 7 + 2 files changed, 154 insertions(+) create mode 100644 Documentation/devicetree/bindings/iommu/riscv,iommu.yaml diff --git a/Documentation/devicetree/bindings/iommu/riscv,iommu.yaml b/Documentation/devicetree/bindings/iommu/riscv,iommu.yaml new file mode 100644 index 000000000000..5d015eeb06d0 --- /dev/null +++ b/Documentation/devicetree/bindings/iommu/riscv,iommu.yaml @@ -0,0 +1,147 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iommu/riscv,iommu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RISC-V IOMMU Architecture Implementation + +maintainers: + - Tomasz Jeznach + +description: | + The RISC-V IOMMU provides memory address translation and isolation for + input and output devices, supporting per-device translation context, + shared process address spaces including the ATS and PRI components of + the PCIe specification, two stage address translation and MSI remapping. + It supports identical translation table format to the RISC-V address + translation tables with page level access and protection attributes. + Hardware uses in-memory command and fault reporting queues with wired + interrupt or MSI notifications. + + Visit https://github.com/riscv-non-isa/riscv-iommu for more details. + + For information on assigning RISC-V IOMMU to its peripheral devices, + see generic IOMMU bindings. + +properties: + # For PCIe IOMMU hardware compatible property should contain the vendor + # and device ID according to the PCI Bus Binding specification. + # Since PCI provides built-in identification methods, compatible is not + # actually required. For non-PCIe hardware implementations 'riscv,iommu' + # should be specified along with 'reg' property providing MMIO location. + compatible: + oneOf: + - items: + - enum: + - qemu,riscv-iommu + - const: riscv,iommu + - items: + - enum: + - pci1efd,edf1 + - const: riscv,pci-iommu + + reg: + maxItems: 1 + description: + For non-PCI devices this represents base address and size of for the + IOMMU memory mapped registers interface. + For PCI IOMMU hardware implementation this should represent an address + of the IOMMU, as defined in the PCI Bus Binding reference. + + '#iommu-cells': + const: 1 + description: + The single cell describes the requester id emitted by a master to the + IOMMU. + + interrupts: + minItems: 1 + maxItems: 4 + description: + Wired interrupt vectors available for RISC-V IOMMU to notify the + RISC-V HARTS. The cause to interrupt vector is software defined + using IVEC IOMMU register. + + msi-parent: true + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - '#iommu-cells' + +additionalProperties: false + +examples: + - |+ + /* Example 1 (IOMMU device with wired interrupts) */ + #include + + iommu1: iommu@1bccd000 { + compatible = "qemu,riscv-iommu", "riscv,iommu"; + reg = <0x1bccd000 0x1000>; + interrupt-parent = <&aplic_smode>; + interrupts = <32 IRQ_TYPE_LEVEL_HIGH>, + <33 IRQ_TYPE_LEVEL_HIGH>, + <34 IRQ_TYPE_LEVEL_HIGH>, + <35 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + }; + + /* Device with two IOMMU device IDs, 0 and 7 */ + master1 { + iommus = <&iommu1 0>, <&iommu1 7>; + }; + + - |+ + /* Example 2 (IOMMU device with shared wired interrupt) */ + #include + + iommu2: iommu@1bccd000 { + compatible = "qemu,riscv-iommu", "riscv,iommu"; + reg = <0x1bccd000 0x1000>; + interrupt-parent = <&aplic_smode>; + interrupts = <32 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + }; + + - |+ + /* Example 3 (IOMMU device with MSIs) */ + iommu3: iommu@1bcdd000 { + compatible = "qemu,riscv-iommu", "riscv,iommu"; + reg = <0x1bccd000 0x1000>; + msi-parent = <&imsics_smode>; + #iommu-cells = <1>; + }; + + - |+ + /* Example 4 (IOMMU PCIe device with MSIs) */ + bus { + #address-cells = <2>; + #size-cells = <2>; + + pcie@30000000 { + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + reg = <0x0 0x30000000 0x0 0x1000000>; + ranges = <0x02000000 0x0 0x41000000 0x0 0x41000000 0x0 0x0f000000>; + + /* + * The IOMMU manages all functions in this PCI domain except + * itself. Omit BDF 00:01.0. + */ + iommu-map = <0x0 &iommu0 0x0 0x8>, + <0x9 &iommu0 0x9 0xfff7>; + + /* The IOMMU programming interface uses slot 00:01.0 */ + iommu0: iommu@1,0 { + compatible = "pci1efd,edf1", "riscv,pci-iommu"; + reg = <0x800 0 0 0 0>; + #iommu-cells = <1>; + }; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index aacccb376c28..0e0cd18d915b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19262,6 +19262,13 @@ F: arch/riscv/ N: riscv K: riscv +RISC-V IOMMU +M: Tomasz Jeznach +L: iommu@lists.linux.dev +L: linux-riscv@lists.infradead.org +S: Maintained +F: Documentation/devicetree/bindings/iommu/riscv,iommu.yaml + RISC-V MICROCHIP FPGA SUPPORT M: Conor Dooley M: Daire McNamara