From patchwork Thu Mar 18 06:08:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greentime Hu X-Patchwork-Id: 12147405 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 067BCC433DB for ; Thu, 18 Mar 2021 06:09:12 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8EBAA64E38 for ; Thu, 18 Mar 2021 06:09:11 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8EBAA64E38 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding :Content-Type:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Cc:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=7BdAIyuyB+I1WBImyY1o9w8iEC3Jtod1amgvlj8/JYA=; b=FWzQHlqLtQ8VE1kdBPmEfH9mf ZqQHhFMSem2UHTAk+Yyg9tbYSQn2xsqVcpeU+omEiOCE4IcncvFXOhAPysCwwVP1uBQanOpOwLHbZ rBP2Z3Y6kYFNN5grcPiLldfO/nhX75o6ncXxmYiME2cr2fp3MKKLv2pyHXhJJZ2QPnWHMJ3tQNIl5 UqDQ9Lk51h2GkG02oJdSSAf1bkh6XWxSYJyJCaOrrtQmQ2Nlo3D45+PQjjbDfxT+tnjgYfLf+fiLI pq0lTRopNg1gYrlZ+wgL6r4HOSNsrf02UH585bBHfcTmRmptdjDYqfYS2E+DbrpIHD0Z+mYbEqY5H 1VuWCaFww==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lMlq2-004aTv-MN; Thu, 18 Mar 2021 06:08:56 +0000 Received: from mail-pf1-x429.google.com ([2607:f8b0:4864:20::429]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lMlpk-004aPR-T9 for linux-riscv@lists.infradead.org; Thu, 18 Mar 2021 06:08:38 +0000 Received: by mail-pf1-x429.google.com with SMTP id x26so2740698pfn.0 for ; Wed, 17 Mar 2021 23:08:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=+Ajx//Hrn2Nysbs5OX32IPY3AqQ7T4AzxnnPGV+AONg=; b=Ep5j77s2uyFhZTdf2aWch6QKWGcwQGf2ydAGmR47fOokZTEPEMazSqbWYDEYuHUf2j gwpMSrzYPEoTtReWWYPWQdT7ksvroeD54vnbeiA5ZTCS7Eox8HjvP9v3qtW5spoM65cF hN0CHfGpceU4Amh8rrVqA01C7+JCznukhEyfcNWlYgFfyXCKXZJZcC2JVUQOECzCxiqK 7gMl7G1zv4TQsmyvVWgHL49wqFNcwpbVosR7MaUZl5VjsemFmNKTRe/5fk19a5Ljyfej yE+jlpGn4h7i6K8lR7QNi9h6nCf8lgZM5QHwI+YifN+kYIDp3vW4AxJNwmEP25ZF9ESU zVaw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+Ajx//Hrn2Nysbs5OX32IPY3AqQ7T4AzxnnPGV+AONg=; b=F9WBmIys+Atu+IlwruBbcFZ1c5EYx4UbY/ZLbPhaDeVFLsmErFPsDu8lWVWM97CIk9 D1c2ax95GRHTeAKguEphWWN5YGAUol5mBIeCV5uwX3hiP5ZZJ9J7G948JqaF9HFYIeSF qZsrEEjYx+NDm03kTulwW46se30TlV4CVlQH4Qm2q3QBeJJwtyKUNw3wxu/dxsIngjfZ dMjTsXZq18iCbSmPN55jT8z8Ii8j/MRmqpvmAbgvqyB/8NlqbijgbZqLt3hnym7vGmwX Rgfw1jJa1TtxNvvuFWbT9ewHhE1s3rfMaoY9zwd2vJI7asApS5LsGXlCQ8XqA1exF63C zajg== X-Gm-Message-State: AOAM531ygL+w+1VwpST3kxpTuYeQhOdWcOur3zdbgbqCkYr4eIL4M5Op jgNCnlWK45GnrnDm4j+q0qOnzg== X-Google-Smtp-Source: ABdhPJxXB321/zc8CA1G6SDaw5CzywX3n3gKzC1wA/MZPyDLcLi67Vz1r2QOR6T5rwIKI3dm8e4YQA== X-Received: by 2002:a63:2c8f:: with SMTP id s137mr5521095pgs.51.1616047715433; Wed, 17 Mar 2021 23:08:35 -0700 (PDT) Received: from hsinchu02.internal.sifive.com (114-34-229-221.HINET-IP.hinet.net. [114.34.229.221]) by smtp.gmail.com with ESMTPSA id 68sm967353pfd.75.2021.03.17.23.08.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Mar 2021 23:08:35 -0700 (PDT) From: Greentime Hu To: greentime.hu@sifive.com, paul.walmsley@sifive.com, hes@sifive.com, erik.danie@sifive.com, zong.li@sifive.com, bhelgaas@google.com, robh+dt@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, mturquette@baylibre.com, sboyd@kernel.org, lorenzo.pieralisi@arm.com, p.zabel@pengutronix.de, alex.dewar90@gmail.com, khilman@baylibre.com, hayashi.kunihiko@socionext.com, vidyas@nvidia.com, jh80.chung@samsung.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, helgaas@kernel.org Subject: [PATCH v2 2/6] clk: sifive: Use reset-simple in prci driver for PCIe driver Date: Thu, 18 Mar 2021 14:08:09 +0800 Message-Id: <91d016e59bab9d9175168a63e7bcd81fdb69b549.1615954046.git.greentime.hu@sifive.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210318_060837_207226_1CC7732E X-CRM114-Status: GOOD ( 15.18 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org We use reset-simple in this patch so that pcie driver can use devm_reset_control_get() to get this reset data structure and use reset_control_deassert() to deassert pcie_power_up_rst_n. Reviewed-by: Philipp Zabel Signed-off-by: Greentime Hu --- drivers/clk/sifive/Kconfig | 2 ++ drivers/clk/sifive/sifive-prci.c | 13 +++++++++++++ drivers/clk/sifive/sifive-prci.h | 4 ++++ drivers/reset/Kconfig | 3 ++- 4 files changed, 21 insertions(+), 1 deletion(-) diff --git a/drivers/clk/sifive/Kconfig b/drivers/clk/sifive/Kconfig index 1c14eb20c066..9132c3c4aa86 100644 --- a/drivers/clk/sifive/Kconfig +++ b/drivers/clk/sifive/Kconfig @@ -10,6 +10,8 @@ if CLK_SIFIVE config CLK_SIFIVE_PRCI bool "PRCI driver for SiFive SoCs" + select RESET_CONTROLLER + select RESET_SIMPLE select CLK_ANALOGBITS_WRPLL_CLN28HPC help Supports the Power Reset Clock interface (PRCI) IP block found in diff --git a/drivers/clk/sifive/sifive-prci.c b/drivers/clk/sifive/sifive-prci.c index baf7313dac92..871ccb287993 100644 --- a/drivers/clk/sifive/sifive-prci.c +++ b/drivers/clk/sifive/sifive-prci.c @@ -583,6 +583,19 @@ static int sifive_prci_probe(struct platform_device *pdev) if (IS_ERR(pd->va)) return PTR_ERR(pd->va); + pd->reset.rcdev.owner = THIS_MODULE; + pd->reset.rcdev.nr_resets = PRCI_RST_NR; + pd->reset.rcdev.ops = &reset_simple_ops; + pd->reset.rcdev.of_node = pdev->dev.of_node; + pd->reset.active_low = true; + pd->reset.membase = pd->va + PRCI_DEVICESRESETREG_OFFSET; + spin_lock_init(&pd->reset.lock); + + r = devm_reset_controller_register(&pdev->dev, &pd->reset.rcdev); + if (r) { + dev_err(dev, "could not register reset controller: %d\n", r); + return r; + } r = __prci_register_clocks(dev, pd, desc); if (r) { dev_err(dev, "could not register clocks: %d\n", r); diff --git a/drivers/clk/sifive/sifive-prci.h b/drivers/clk/sifive/sifive-prci.h index 022c67cf053c..91658a88af4e 100644 --- a/drivers/clk/sifive/sifive-prci.h +++ b/drivers/clk/sifive/sifive-prci.h @@ -11,6 +11,7 @@ #include #include +#include #include /* @@ -121,6 +122,8 @@ #define PRCI_DEVICESRESETREG_CHIPLINK_RST_N_MASK \ (0x1 << PRCI_DEVICESRESETREG_CHIPLINK_RST_N_SHIFT) +#define PRCI_RST_NR 7 + /* CLKMUXSTATUSREG */ #define PRCI_CLKMUXSTATUSREG_OFFSET 0x2c #define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT 1 @@ -221,6 +224,7 @@ */ struct __prci_data { void __iomem *va; + struct reset_simple_data reset; struct clk_hw_onecell_data hw_clks; }; diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 71ab75a46491..f094df93d911 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -173,7 +173,7 @@ config RESET_SCMI config RESET_SIMPLE bool "Simple Reset Controller Driver" if COMPILE_TEST - default ARCH_AGILEX || ARCH_ASPEED || ARCH_BITMAIN || ARCH_REALTEK || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARC + default ARCH_AGILEX || ARCH_ASPEED || ARCH_BITMAIN || ARCH_REALTEK || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARC || RISCV help This enables a simple reset controller driver for reset lines that that can be asserted and deasserted by toggling bits in a contiguous, @@ -187,6 +187,7 @@ config RESET_SIMPLE - RCC reset controller in STM32 MCUs - Allwinner SoCs - ZTE's zx2967 family + - SiFive FU740 SoCs config RESET_STM32MP157 bool "STM32MP157 Reset Driver" if COMPILE_TEST