[04/17] riscv: Add vector feature to compile

Message ID	CAM2SziULUhiERdo2m8jSHu7jCN9bHXUmvjPO1P_MP1wLrD__Xg@mail.gmail.com (mailing list archive)
State	Superseded
Headers	show Return-Path: <linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org> MIME-Version: 1.0 From: Chris Stillson <stillson@rivosinc.com> Date: Wed, 21 Sep 2022 09:47:08 -0700 Message-ID: <CAM2SziULUhiERdo2m8jSHu7jCN9bHXUmvjPO1P_MP1wLrD__Xg@mail.gmail.com> Subject: [PATCH 04/17] riscv: Add vector feature to compile To: linux-riscv@lists.infradead.org Cc: palmer@dabbelt.com Precedence: list Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" <linux-riscv-bounces@lists.infradead.org> Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org
Series	Prctl to enable vector commands, previous vector patches rebased \| expand [00/17] Prctl to enable vector commands, previous vector patches rebased [01/17] riscv: Rename __switch_to_aux -> fpu [02/17] riscv: Extending cpufeature.c to detect V-extension [03/17] riscv: Add new csr defines related to vector extension [04/17] riscv: Add vector feature to compile [05/17] riscv: Add has_vector/riscv_vsize to save vector features. [06/17] riscv: Reset vector register [07/17] riscv: Add vector struct and assembler definitions [08/17] riscv: Add task switch support for vector [09/17] riscv: Add ptrace vector support [10/17] riscv: Add sigcontext save/restore for vector [11/17] riscv: signal: Report signal frame size to userspace via auxv [12/17] riscv: Add support for kernel mode vector [13/17] riscv: Add vector extension XOR implementation [14/17] riscv: Fix a kernel panic issue if $s2 is set to a specific value before entering Linux [15/17] riscv: Add V extension to KVM ISA allow list [16/17] riscv: KVM: Add vector lazy save/restore support [17/17] riscv: prctl to enable vector commands

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CAM2SziULUhiERdo2m8jSHu7jCN9bHXUmvjPO1P_MP1wLrD__Xg@mail.gmail.com (mailing list archive)

State

Superseded

Headers

MIME-Version: 1.0
From: Chris Stillson <stillson@rivosinc.com>
Date: Wed, 21 Sep 2022 09:47:08 -0700
Message-ID: 
 <CAM2SziULUhiERdo2m8jSHu7jCN9bHXUmvjPO1P_MP1wLrD__Xg@mail.gmail.com>
Subject: [PATCH 04/17] riscv: Add vector feature to compile
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Cc: palmer@dabbelt.com
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Series

Prctl to enable vector commands, previous vector patches rebased | expand

Commit Message

Chris Stillson Sept. 21, 2022, 4:47 p.m. UTC

This patch adds a new config option which could enable assembler's
vector feature.

Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Co-developed-by: Greentime Hu <greentime.hu@sifive.com>
Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
---
 arch/riscv/Kconfig  | 15 +++++++++++++--
 arch/riscv/Makefile |  1 +
 2 files changed, 14 insertions(+), 2 deletions(-)

--
2.25.1

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index ed66c31e4655..e294d85bfb7d 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -432,7 +432,17 @@  config FPU

          If you don't know what to do here, say Y.

-endmenu # "Platform type"
+config VECTOR
+       bool "VECTOR support"
+       depends on GCC_VERSION >= 120000 || CLANG_VERSION >= 130000
+       default n
+       help
+         Say N here if you want to disable all vector related procedure
+         in the kernel.
+
+         If you don't know what to do here, say Y.
+
+endmenu

 menu "Kernel features"

@@ -556,6 +566,7 @@  config CMDLINE_EXTEND
          cases where the provided arguments are insufficient and
          you don't want to or cannot modify them.

+
 config CMDLINE_FORCE
        bool "Always use the default kernel command string"
        help
@@ -648,7 +659,7 @@  config XIP_PHYS_ADDR
          be linked for and stored to.  This address is dependent on your
          own flash usage.

-endmenu # "Boot options"
+endmenu

 config BUILTIN_DTB
        bool
diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
index 3fa8ef336822..1ec17f3d6d09 100644
--- a/arch/riscv/Makefile
+++ b/arch/riscv/Makefile
@@ -50,6 +50,7 @@  riscv-march-$(CONFIG_ARCH_RV32I)      := rv32ima
 riscv-march-$(CONFIG_ARCH_RV64I)       := rv64ima
 riscv-march-$(CONFIG_FPU)              := $(riscv-march-y)fd
 riscv-march-$(CONFIG_RISCV_ISA_C)      := $(riscv-march-y)c
+riscv-march-$(CONFIG_VECTOR)           := $(riscv-march-y)v

 # Newer binutils versions default to ISA spec version 20191213 which moves some
 # instructions from the I extension to the Zicsr and Zifencei extensions.

[04/17] riscv: Add vector feature to compile

Commit Message

Patch