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Mon, 13 Nov 2023 09:25:59 +0000 Received: from IA1PR20MB4953.namprd20.prod.outlook.com ([fe80::55b:c350:980:ad8]) by IA1PR20MB4953.namprd20.prod.outlook.com ([fe80::55b:c350:980:ad8%6]) with mapi id 15.20.6977.029; Mon, 13 Nov 2023 09:25:59 +0000 From: Inochi Amaoto To: Chao Wei , Chen Wang , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Jisheng Zhang Cc: Inochi Amaoto , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH] riscv: dts: sophgo: remove address-cells from CV1800B intc node Date: Mon, 13 Nov 2023 17:26:15 +0800 Message-ID: X-Mailer: git-send-email 2.42.1 X-TMN: [wEvxMjLbPiEQh6PPG7qWkwPTA10ApsD5A5yMO0pAxcQ=] X-ClientProxiedBy: SJ0PR05CA0125.namprd05.prod.outlook.com (2603:10b6:a03:33d::10) To IA1PR20MB4953.namprd20.prod.outlook.com (2603:10b6:208:3af::19) X-Microsoft-Original-Message-ID: <20231113092617.114031-1-inochiama@outlook.com> MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: IA1PR20MB4953:EE_|MW3PR20MB3465:EE_ X-MS-Office365-Filtering-Correlation-Id: 83675bb7-ab93-4bf7-d2ac-08dbe42a8b9a X-Microsoft-Antispam: BCL:0; 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X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org A recent submission from Rob has added additionalProperties: false to the interrupt-controller child node of RISC-V cpus. But CV1800B does not follow this change and still uses #address-cells in its interrupt controller. As it has no child nodes, #address-cells is not needed and can be removed. Fixes: c3dffa879cca ("riscv: dts: sophgo: add initial CV1800B SoC device tree") Link: https://patchwork.kernel.org/project/linux-riscv/patch/20230915201946.4184468-1-robh@kernel.org/ Signed-off-by: Inochi Amaoto --- arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 1 - 1 file changed, 1 deletion(-) -- 2.42.1 diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi index df40e87ee063..aec6401a467b 100644 --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi @@ -34,7 +34,6 @@ cpu0: cpu@0 { cpu0_intc: interrupt-controller { compatible = "riscv,cpu-intc"; interrupt-controller; - #address-cells = <0>; #interrupt-cells = <1>; }; };