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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 72ccEPmFxyu3JYVa5s4l3Tb6fW3wT7tQCTkJteyQlQRE3YnDs42SlZEhCC4mFNbFl6mZ5vQ9okV+JWfYaINE8dIfveF9hLlQlu66mMdLFRWRIgZdbTYLHWbOGG+BxE3DLyGiy+TGHFA/BZfUU7JPbpmgJyy22NyKZrjbd8zW5DzHpeaBoaWL0nGfMpI5j0iM46r+mTzclOI5vuMXTwGobH0+EZ0sRFc291zO9laNXphFZOWgmLO+mOEooVXBl3iYp/pa4sGBT4CLUOEazrYCjcXvppwxqiEbSID+swPQbvkQ02bXHH7BxGv7elc00i6JJj22Y36Tlygo+8l/JqkEEHN56WzuFg/O7TTNgPUz09OkhhRb4hc1QnGDt8Dwt8Zr31+FCqBMpKZtqJlKNT3o+EgLdMHscsnkXZLMWV81Y7OJVunnO/WhUBNfJEyZKwSfTynxznFQqLD+7rcfjjMEbZALQtdA/LjruY3pchiBKc/z2mj74jbZ6wJnHLhFPjA+ysZi3p/6zmtLiSWQtQz2VuN/GHwiXp4UyoYmqc1Fu3xsczUJE9zG9Wbg8DCv8yQ0m0fuYKDJPcWMDr5dCT9XrlU0B3o0JtVI0Yt+aU1jHi/UnaN853DSHSwaqXcT80rkTOmN6lZ9kSbYUDd1sDm1Un7hgs62A7Fp955WzGptVxE61hPVyuxQ4rzxhP6LmXtWzQqmDBu5e0G+8da1rFsb7gvzxxwainR52pzX1wdsFIMXJOmZd+qJhpRGkuPxzTPmnhQcIFCrhaWLOOR0rqxWJHjsrVV8BAqHJe/9UZFaKkONUUDRs5OoLNYKx5pJ5My8grk21w4DliaeKcXnXRAnABycJsuFlMviZqGPsq5YJXDmBlCOA7Cf2upY1sU6UKogioZQZQqFmzZO60e00p94U0wUeuTYR4UDcv0jq1xI5+jd1759jygqnIuq9Q4m2DlkCe+YYy9yBJw1LRsFUOV9u1Uk4Zn/F20lYD3cSRdlY3q7vAHFq2Pex7uCWSX+PjUebQ1eOx1ydj75L33W0uOCOseFcQ7B/jMZv8L5nDgppx2YkO8BBe88MXxYDxKMU5wd5cLhvuOVGSL+8IFa8R1KTfjHasrWIUjo26/KvqYPLbOTX43pj/E5GG1t+fzA/B1dqUx3V95nJH9NfMihnkNlscu4SXkoLU8VcWJihgaR/3G6e7IrJCwHXkp6FT71/deBCaQPyBHWXudAakuLNOYImzOlBvYEdygLPmOsKO82+ZZQol76v2mX3yiZD6iBrA7VeRUCwGlsWdVidoTPWsTD+lN9XlsaMrdtZsrT97lYhmU/mZlPD4ktJ2EHl3cLGRGuwUk2VFxbr+6mx/x+4Ac/r55zKEIkU4JX4EhTkK/WwPNmiC2lsRmW/tzHmATWJ7qAmw/A82u9K81Rgkb0tD2qhv/XQ7FA4WBgGaPp+MwndffTHB+Xhu23/K38EZyeZD5L4ALb77iyB7DI6tilgGDc9nTZUlI9xFVly+HASYFOQsaVx+jQfasAp1IXxqR0FtmPfkyFGQ5Mg9xo0XqaqsFDv88A72nQuLtILyyrVedm8gjlPG7/x6xFcooBbWhDBX7sXmVqp8qzwmuztBBF7cqh7GJkjG/MszPN517piaw3AMbGYAURbCFvOw7Ir/ZovrODSSCtyS/3yh48RZ/h4QAAa6/X3MKf/LYGuPBOPR1Y3iC6Aq0p9YPtrfQgL3ZD3hcaXXEJHcvKKhpc5n6fXSItXw== X-OriginatorOrg: zenithal.me X-MS-Exchange-CrossTenant-Network-Message-Id: a8adcbdc-7f87-4771-a3a8-08da4ca3e474 X-MS-Exchange-CrossTenant-AuthSource: TYCP286MB1393.JPNP286.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Jun 2022 18:46:42.5387 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 436d481c-43b1-4418-8d7f-84c1e4887cf0 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: R50NL+1EL2nhqSl2wvcDOstg3ctZapYmQUWktGc1llzEL7FBb+1NWtXfJ5X1Tfm0 X-MS-Exchange-Transport-CrossTenantHeadersStamped: OSZP286MB1063 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220612_114649_321323_F49CF25A X-CRM114-Status: GOOD ( 11.00 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org userspace currently lacks a way to detect whether the platform has Bitmanip/Scalar Crypto capability, this patch adds an interface such that the userspace can detect it. RISC-V currently still has no mature mechanism, but no matter how things in the spec changes, (no matter how "M" mode things change), the kernel still needs to offer some API to the userspace. More discussion can be found at https://github.com/openssl/openssl/pull/18197 In short, userspace currently has to use env var to detect them. This interface does not make any assumptions about the underlying hardware Tested-by: Jiatai He Signed-off-by: Hongren (Zenithal) Zheng --- arch/riscv/include/uapi/asm/hwcap.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/riscv/include/uapi/asm/hwcap.h b/arch/riscv/include/uapi/asm/hwcap.h index 46dc3f5ee99f..bfed3e5c338c 100644 --- a/arch/riscv/include/uapi/asm/hwcap.h +++ b/arch/riscv/include/uapi/asm/hwcap.h @@ -22,4 +22,26 @@ #define COMPAT_HWCAP_ISA_D (1 << ('D' - 'A')) #define COMPAT_HWCAP_ISA_C (1 << ('C' - 'A')) +/* + * HWCAP2 flags - for elf_hwcap2 (in kernel) and AT_HWCAP2 + * + * As only 32 bits of elf_hwcap (in kernel) could be used + * and RISC-V has reserved 26 bits of it, other caps like + * bitmanip and crypto can not be placed in AT_HWCAP + */ +#define COMPAT_HWCAP2_ISA_ZBA (1 << 0) +#define COMPAT_HWCAP2_ISA_ZBB (1 << 1) +#define COMPAT_HWCAP2_ISA_ZBC (1 << 2) +#define COMPAT_HWCAP2_ISA_ZBS (1 << 3) +#define COMPAT_HWCAP2_ISA_ZBKB (1 << 4) +#define COMPAT_HWCAP2_ISA_ZBKC (1 << 5) +#define COMPAT_HWCAP2_ISA_ZBKX (1 << 6) +#define COMPAT_HWCAP2_ISA_ZKND (1 << 7) +#define COMPAT_HWCAP2_ISA_ZKNE (1 << 8) +#define COMPAT_HWCAP2_ISA_ZKNH (1 << 9) +#define COMPAT_HWCAP2_ISA_ZKSED (1 << 10) +#define COMPAT_HWCAP2_ISA_ZKSH (1 << 11) +#define COMPAT_HWCAP2_ISA_ZKR (1 << 12) +#define COMPAT_HWCAP2_ISA_ZKT (1 << 13) + #endif /* _UAPI_ASM_RISCV_HWCAP_H */