Message ID | a9b213536c5bbc20de649afae69d2898a75924e4.1736923025.git.unicorn_wang@outlook.com (mailing list archive) |
---|---|
State | Handled Elsewhere |
Headers | show |
Series | Add PCIe support to Sophgo SG2042 SoC | expand |
On Wed, 15 Jan 2025 15:07:14 +0800, Chen Wang wrote: > Document SOPHGO SG2042 compatible for PCIe control registers. > These registers are shared by PCIe controller nodes. > > Applied, thanks! [3/5] dt-bindings: mfd: syscon: Add sg2042 pcie ctrl compatible commit: 28df3b1a6aeced4c77a70adc12b4d7b0b69e2ea6 -- Lee Jones [李琼斯]
Hello, Lee I would request that this patch not be merged yet, because it is related to PCIe changes, and the PCIe changes (bindings and dts) have not been confirmed yet. Although this patch is small and will not affect other builds, it is best to submit it together with the PCIe patch after it is confirmed. Sorry for the trouble. Best regards Chen On 2025/2/11 22:33, Lee Jones wrote: > On Wed, 15 Jan 2025 15:07:14 +0800, Chen Wang wrote: >> Document SOPHGO SG2042 compatible for PCIe control registers. >> These registers are shared by PCIe controller nodes. >> >> > Applied, thanks! > > [3/5] dt-bindings: mfd: syscon: Add sg2042 pcie ctrl compatible > commit: 28df3b1a6aeced4c77a70adc12b4d7b0b69e2ea6 > > -- > Lee Jones [李琼斯] >
diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml index b414de4fa779..afd89aa0ae8b 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -107,6 +107,7 @@ select: - rockchip,rk3576-qos - rockchip,rk3588-qos - rockchip,rv1126-qos + - sophgo,sg2042-pcie-ctrl - st,spear1340-misc - stericsson,nomadik-pmu - starfive,jh7100-sysmain @@ -205,6 +206,7 @@ properties: - rockchip,rk3576-qos - rockchip,rk3588-qos - rockchip,rv1126-qos + - sophgo,sg2042-pcie-ctrl - st,spear1340-misc - stericsson,nomadik-pmu - starfive,jh7100-sysmain