diff mbox series

[v3,3/5] dt-bindings: mfd: syscon: Add sg2042 pcie ctrl compatible

Message ID a9b213536c5bbc20de649afae69d2898a75924e4.1736923025.git.unicorn_wang@outlook.com (mailing list archive)
State Handled Elsewhere
Headers show
Series Add PCIe support to Sophgo SG2042 SoC | expand

Checks

Context Check Description
conchuod/vmtest-for-next-PR fail PR summary
conchuod/patch-3-test-1 success .github/scripts/patches/tests/build_rv32_defconfig.sh took 103.75s
conchuod/patch-3-test-2 success .github/scripts/patches/tests/build_rv64_clang_allmodconfig.sh took 1000.71s
conchuod/patch-3-test-3 success .github/scripts/patches/tests/build_rv64_gcc_allmodconfig.sh took 1187.10s
conchuod/patch-3-test-4 success .github/scripts/patches/tests/build_rv64_nommu_k210_defconfig.sh took 17.97s
conchuod/patch-3-test-5 success .github/scripts/patches/tests/build_rv64_nommu_virt_defconfig.sh took 19.65s
conchuod/patch-3-test-6 success .github/scripts/patches/tests/checkpatch.sh took 0.43s
conchuod/patch-3-test-7 success .github/scripts/patches/tests/dtb_warn_rv64.sh took 38.67s
conchuod/patch-3-test-8 success .github/scripts/patches/tests/header_inline.sh took 0.00s
conchuod/patch-3-test-9 success .github/scripts/patches/tests/kdoc.sh took 0.52s
conchuod/patch-3-test-10 success .github/scripts/patches/tests/module_param.sh took 0.01s
conchuod/patch-3-test-11 success .github/scripts/patches/tests/verify_fixes.sh took 0.00s
conchuod/patch-3-test-12 success .github/scripts/patches/tests/verify_signedoff.sh took 0.03s

Commit Message

Chen Wang Jan. 15, 2025, 7:07 a.m. UTC
From: Chen Wang <unicorn_wang@outlook.com>

Document SOPHGO SG2042 compatible for PCIe control registers.
These registers are shared by PCIe controller nodes.

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
---
 Documentation/devicetree/bindings/mfd/syscon.yaml | 2 ++
 1 file changed, 2 insertions(+)

Comments

Lee Jones Feb. 11, 2025, 2:33 p.m. UTC | #1
On Wed, 15 Jan 2025 15:07:14 +0800, Chen Wang wrote:
> Document SOPHGO SG2042 compatible for PCIe control registers.
> These registers are shared by PCIe controller nodes.
> 
> 

Applied, thanks!

[3/5] dt-bindings: mfd: syscon: Add sg2042 pcie ctrl compatible
      commit: 28df3b1a6aeced4c77a70adc12b4d7b0b69e2ea6

--
Lee Jones [李琼斯]
Chen Wang Feb. 12, 2025, 12:48 a.m. UTC | #2
Hello, Lee

I would request that this patch not be merged yet, because it is related 
to PCIe changes, and the PCIe changes (bindings and dts) have not been 
confirmed yet.

Although this patch is small and will not affect other builds, it is 
best to submit it together with the PCIe patch after it is confirmed.

Sorry for the trouble.

Best regards

Chen

On 2025/2/11 22:33, Lee Jones wrote:
> On Wed, 15 Jan 2025 15:07:14 +0800, Chen Wang wrote:
>> Document SOPHGO SG2042 compatible for PCIe control registers.
>> These registers are shared by PCIe controller nodes.
>>
>>
> Applied, thanks!
>
> [3/5] dt-bindings: mfd: syscon: Add sg2042 pcie ctrl compatible
>        commit: 28df3b1a6aeced4c77a70adc12b4d7b0b69e2ea6
>
> --
> Lee Jones [李琼斯]
>
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml
index b414de4fa779..afd89aa0ae8b 100644
--- a/Documentation/devicetree/bindings/mfd/syscon.yaml
+++ b/Documentation/devicetree/bindings/mfd/syscon.yaml
@@ -107,6 +107,7 @@  select:
           - rockchip,rk3576-qos
           - rockchip,rk3588-qos
           - rockchip,rv1126-qos
+          - sophgo,sg2042-pcie-ctrl
           - st,spear1340-misc
           - stericsson,nomadik-pmu
           - starfive,jh7100-sysmain
@@ -205,6 +206,7 @@  properties:
           - rockchip,rk3576-qos
           - rockchip,rk3588-qos
           - rockchip,rv1126-qos
+          - sophgo,sg2042-pcie-ctrl
           - st,spear1340-misc
           - stericsson,nomadik-pmu
           - starfive,jh7100-sysmain