Message ID | c9dd12c3ad77b13dcdfbf4accd51e92e6ea2a4a9.1736921549.git.unicorn_wang@outlook.com (mailing list archive) |
---|---|
State | Handled Elsewhere |
Headers | show |
Series | irqchip: Add Sophgo SG2042 MSI controller | expand |
On Wed, Jan 15, 2025 at 02:33:23PM +0800, Chen Wang wrote: > From: Chen Wang <unicorn_wang@outlook.com> > > Add binding for Sophgo SG2042 MSI controller. > > Signed-off-by: Chen Wang <unicorn_wang@outlook.com> > --- > .../sophgo,sg2042-msi.yaml | 58 +++++++++++++++++++ > 1 file changed, 58 insertions(+) > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-msi.yaml > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-msi.yaml b/Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-msi.yaml > new file mode 100644 > index 000000000000..f641df191787 > --- /dev/null > +++ b/Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-msi.yaml > @@ -0,0 +1,58 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/interrupt-controller/sophgo,sg2042-msi.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Sophgo SG2042 MSI Controller > + > +maintainers: > + - Chen Wang <unicorn_wang@outlook.com> > + > +description: > + This interrupt controller is in Sophgo SG2042 for transforming interrupts from > + PCIe MSI to PLIC interrupts. > + > +allOf: > + - $ref: /schemas/interrupts.yaml# > + - $ref: /schemas/interrupt-controller/msi-controller.yaml# > + > +properties: > + compatible: > + const: sophgo,sg2042-msi > + > + reg: > + items: > + - description: msi doorbell address > + - description: clear register > + > + reg-names: > + items: > + - const: doorbell > + - const: clr please reverse the items order, the clr addr is more suitable as the MMIO device address when writing device node. doorbeel address is just a IO address and can not be seen from CPU. > + > + msi-controller: true > + > + msi-ranges: > + maxItems: 1 > + > +required: > + - compatible > + - reg > + - reg-names > + - msi-controller > + - msi-ranges > + > +unevaluatedProperties: false > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/irq.h> > + msi-controller@30000000 { > + compatible = "sophgo,sg2042-msi"; > + reg = <0x30000000 0x4>, <0x30000008 0x4>; > + reg-names = "doorbell", "clr"; > + msi-controller; > + msi-ranges = <&plic 64 IRQ_TYPE_LEVEL_HIGH 32>; > + interrupt-parent = <&plic>; > + }; > -- > 2.34.1 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv
On 2025/1/20 10:42, Inochi Amaoto wrote: > On Wed, Jan 15, 2025 at 02:33:23PM +0800, Chen Wang wrote: [......] >> + reg: >> + items: >> + - description: msi doorbell address >> + - description: clear register >> + >> + reg-names: >> + items: >> + - const: doorbell >> + - const: clr > please reverse the items order, the clr addr is more suitable > as the MMIO device address when writing device node. doorbeel > address is just a IO address and can not be seen from CPU. I find dtbcheck will report error if order is switched. On SG2042, address of doorbell is ahead of clr. >> + >> + msi-controller: true >> + >> + msi-ranges: >> + maxItems: 1 >> + >> +required: >> + - compatible >> + - reg >> + - reg-names >> + - msi-controller >> + - msi-ranges >> + >> +unevaluatedProperties: false >> + >> +examples: >> + - | >> + #include <dt-bindings/interrupt-controller/irq.h> >> + msi-controller@30000000 { >> + compatible = "sophgo,sg2042-msi"; >> + reg = <0x30000000 0x4>, <0x30000008 0x4>; >> + reg-names = "doorbell", "clr"; >> + msi-controller; >> + msi-ranges = <&plic 64 IRQ_TYPE_LEVEL_HIGH 32>; >> + interrupt-parent = <&plic>; >> + }; >> -- >> 2.34.1 >> >> >> _______________________________________________ >> linux-riscv mailing list >> linux-riscv@lists.infradead.org >> http://lists.infradead.org/mailman/listinfo/linux-riscv
On Wed, Jan 22, 2025 at 09:51:05PM +0800, Chen Wang wrote: > > On 2025/1/20 10:42, Inochi Amaoto wrote: > > On Wed, Jan 15, 2025 at 02:33:23PM +0800, Chen Wang wrote: > [......] > > > + reg: > > > + items: > > > + - description: msi doorbell address > > > + - description: clear register > > > + > > > + reg-names: > > > + items: > > > + - const: doorbell > > > + - const: clr > > please reverse the items order, the clr addr is more suitable > > as the MMIO device address when writing device node. doorbeel > > address is just a IO address and can not be seen from CPU. > > I find dtbcheck will report error if order is switched. > You should also change the unit address to avoid error. I think you forgot it. > On SG2042, address of doorbell is ahead of clr. > It is the same on SG2044, but there is a problem that the doorbell addr is a IO address and it is not suitable to represent the device addr in the dtb. It also lead to a weird unit address on SG2044 which is hard to understand. Regards, Inochi
On 2025/1/23 6:42, Inochi Amaoto wrote: > On Wed, Jan 22, 2025 at 09:51:05PM +0800, Chen Wang wrote: >> On 2025/1/20 10:42, Inochi Amaoto wrote: >>> On Wed, Jan 15, 2025 at 02:33:23PM +0800, Chen Wang wrote: >> [......] >>>> + reg: >>>> + items: >>>> + - description: msi doorbell address >>>> + - description: clear register >>>> + >>>> + reg-names: >>>> + items: >>>> + - const: doorbell >>>> + - const: clr >>> please reverse the items order, the clr addr is more suitable >>> as the MMIO device address when writing device node. doorbeel >>> address is just a IO address and can not be seen from CPU. >> I find dtbcheck will report error if order is switched. >> > You should also change the unit address to avoid error. > I think you forgot it. I forgot it, thanks for your suggestion. >> On SG2042, address of doorbell is ahead of clr. >> > It is the same on SG2044, but there is a problem that the > doorbell addr is a IO address and it is not suitable to > represent the device addr in the dtb. It also lead to a > weird unit address on SG2044 which is hard to understand. > > Regards, > Inochi
On Wed, Jan 15, 2025 at 02:33:23PM +0800, Chen Wang wrote: > From: Chen Wang <unicorn_wang@outlook.com> > > Add binding for Sophgo SG2042 MSI controller. > > Signed-off-by: Chen Wang <unicorn_wang@outlook.com> > --- > .../sophgo,sg2042-msi.yaml | 58 +++++++++++++++++++ > 1 file changed, 58 insertions(+) > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-msi.yaml > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-msi.yaml b/Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-msi.yaml > new file mode 100644 > index 000000000000..f641df191787 > --- /dev/null > +++ b/Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-msi.yaml > @@ -0,0 +1,58 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/interrupt-controller/sophgo,sg2042-msi.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Sophgo SG2042 MSI Controller > + > +maintainers: > + - Chen Wang <unicorn_wang@outlook.com> > + > +description: > + This interrupt controller is in Sophgo SG2042 for transforming interrupts from > + PCIe MSI to PLIC interrupts. > + > +allOf: > + - $ref: /schemas/interrupts.yaml# Drop this. > + - $ref: /schemas/interrupt-controller/msi-controller.yaml# > + > +properties: > + compatible: > + const: sophgo,sg2042-msi > + > + reg: > + items: > + - description: msi doorbell address > + - description: clear register > + > + reg-names: > + items: > + - const: doorbell > + - const: clr > + > + msi-controller: true > + > + msi-ranges: > + maxItems: 1 You need #msi-cells. > + > +required: > + - compatible > + - reg > + - reg-names > + - msi-controller > + - msi-ranges > + > +unevaluatedProperties: false > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/irq.h> > + msi-controller@30000000 { > + compatible = "sophgo,sg2042-msi"; > + reg = <0x30000000 0x4>, <0x30000008 0x4>; > + reg-names = "doorbell", "clr"; > + msi-controller; > + msi-ranges = <&plic 64 IRQ_TYPE_LEVEL_HIGH 32>; > + interrupt-parent = <&plic>; > + }; > -- > 2.34.1 >
hello, Rob, On 2025/1/24 5:29, Rob Herring wrote: > On Wed, Jan 15, 2025 at 02:33:23PM +0800, Chen Wang wrote: >> From: Chen Wang <unicorn_wang@outlook.com> >> >> Add binding for Sophgo SG2042 MSI controller. >> >> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> >> --- >> .../sophgo,sg2042-msi.yaml | 58 +++++++++++++++++++ >> 1 file changed, 58 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-msi.yaml >> >> diff --git a/Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-msi.yaml b/Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-msi.yaml >> new file mode 100644 >> index 000000000000..f641df191787 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-msi.yaml >> @@ -0,0 +1,58 @@ >> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/interrupt-controller/sophgo,sg2042-msi.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Sophgo SG2042 MSI Controller >> + >> +maintainers: >> + - Chen Wang <unicorn_wang@outlook.com> >> + >> +description: >> + This interrupt controller is in Sophgo SG2042 for transforming interrupts from >> + PCIe MSI to PLIC interrupts. >> + >> +allOf: >> + - $ref: /schemas/interrupts.yaml# > Drop this. I find if we drop this line, dtb check will report "Unevaluated properties are not allowed ('interrupt-parent' was unexpected)" Do we still need to keep this? Thanks, Chen >> + - $ref: /schemas/interrupt-controller/msi-controller.yaml# >> + >> +properties: >> + compatible: >> + const: sophgo,sg2042-msi >> + >> + reg: >> + items: >> + - description: msi doorbell address >> + - description: clear register >> + >> + reg-names: >> + items: >> + - const: doorbell >> + - const: clr >> + >> + msi-controller: true >> + >> + msi-ranges: >> + maxItems: 1 > You need #msi-cells. OK, will add this. >> + >> +required: >> + - compatible >> + - reg >> + - reg-names >> + - msi-controller >> + - msi-ranges >> + >> +unevaluatedProperties: false >> + >> +examples: >> + - | >> + #include <dt-bindings/interrupt-controller/irq.h> >> + msi-controller@30000000 { >> + compatible = "sophgo,sg2042-msi"; >> + reg = <0x30000000 0x4>, <0x30000008 0x4>; >> + reg-names = "doorbell", "clr"; >> + msi-controller; >> + msi-ranges = <&plic 64 IRQ_TYPE_LEVEL_HIGH 32>; >> + interrupt-parent = <&plic>; >> + }; >> -- >> 2.34.1 >>
diff --git a/Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-msi.yaml b/Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-msi.yaml new file mode 100644 index 000000000000..f641df191787 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-msi.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/sophgo,sg2042-msi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo SG2042 MSI Controller + +maintainers: + - Chen Wang <unicorn_wang@outlook.com> + +description: + This interrupt controller is in Sophgo SG2042 for transforming interrupts from + PCIe MSI to PLIC interrupts. + +allOf: + - $ref: /schemas/interrupts.yaml# + - $ref: /schemas/interrupt-controller/msi-controller.yaml# + +properties: + compatible: + const: sophgo,sg2042-msi + + reg: + items: + - description: msi doorbell address + - description: clear register + + reg-names: + items: + - const: doorbell + - const: clr + + msi-controller: true + + msi-ranges: + maxItems: 1 + +required: + - compatible + - reg + - reg-names + - msi-controller + - msi-ranges + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + msi-controller@30000000 { + compatible = "sophgo,sg2042-msi"; + reg = <0x30000000 0x4>, <0x30000008 0x4>; + reg-names = "doorbell", "clr"; + msi-controller; + msi-ranges = <&plic 64 IRQ_TYPE_LEVEL_HIGH 32>; + interrupt-parent = <&plic>; + };