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AJvYcCXZzLJ3KrBnhvsZBKHhffJoylp9THXKoBnuKb68/w/uy0P/WPsKKbWj5H0D2qGKPB8xXuC5dc89RTLZqnI0GkSlyC8N9b+4jU7Go4/iA0Kn X-Gm-Message-State: AOJu0YyFFVw0QJC5w3ZFKNYq+KyhRyRDJYXWOpk+i5FIhPSj1R1kfgS6 vow67Ifdgp8qrjOVk0/vkpxEP8pfF+TeU7mima6TtLeHudXSPdyU X-Google-Smtp-Source: AGHT+IFALoxJytTixSUwVOhyfDsBA+wYcZg2xiod4lujmIbAlaE/efLxS/7TXcwcLL+d05UFBkl5gw== X-Received: by 2002:a05:6830:1e70:b0:6f9:f231:3909 with SMTP id 46e09a7af769-6fb939f0984mr12894884a34.29.1718699919166; Tue, 18 Jun 2024 01:38:39 -0700 (PDT) Received: from localhost.localdomain ([122.8.183.87]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-6fb5b1b0bd9sm1779441a34.27.2024.06.18.01.38.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Jun 2024 01:38:37 -0700 (PDT) From: Chen Wang To: adrian.hunter@intel.com, aou@eecs.berkeley.edu, conor+dt@kernel.org, guoren@kernel.org, inochiama@outlook.com, jszhang@kernel.org, krzysztof.kozlowski+dt@linaro.org, palmer@dabbelt.com, paul.walmsley@sifive.com, robh@kernel.org, ulf.hansson@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-riscv@lists.infradead.org, chao.wei@sophgo.com, haijiao.liu@sophgo.com, xiaoguang.xing@sophgo.com, tingzhu.wang@sophgo.com Cc: Chen Wang Subject: [PATCH v4 2/4] dt-bindings: mmc: sdhci-of-dwcmhsc: Add Sophgo SG2042 support Date: Tue, 18 Jun 2024 16:38:30 +0800 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240618_013840_513310_6C349B06 X-CRM114-Status: GOOD ( 10.60 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Chen Wang SG2042 use Synopsys dwcnshc IP for SD/eMMC controllers. SG2042 defines 3 clocks for SD/eMMC controllers. - AXI_EMMC/AXI_SD for aclk/hclk(Bus interface clocks in DWC_mshc) and blck(Core Base Clock in DWC_mshc), these 3 clocks share one source, so reuse existing "core". - 100K_EMMC/100K_SD for cqetmclk(Timer clocks in DWC_mshc), so reuse existing "timer" which was added for rockchip specified. - EMMC_100M/SD_100M for cclk(Card clocks in DWC_mshc), add new "card". Adding example for sg2042. Signed-off-by: Chen Wang --- .../bindings/mmc/snps,dwcmshc-sdhci.yaml | 69 +++++++++++++------ 1 file changed, 49 insertions(+), 20 deletions(-) diff --git a/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml b/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml index 4d3031d9965f..b53f20733f79 100644 --- a/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml +++ b/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml @@ -21,6 +21,7 @@ properties: - snps,dwcmshc-sdhci - sophgo,cv1800b-dwcmshc - sophgo,sg2002-dwcmshc + - sophgo,sg2042-dwcmshc - thead,th1520-dwcmshc reg: @@ -29,25 +30,6 @@ properties: interrupts: maxItems: 1 - clocks: - minItems: 1 - items: - - description: core clock - - description: bus clock for optional - - description: axi clock for rockchip specified - - description: block clock for rockchip specified - - description: timer clock for rockchip specified - - - clock-names: - minItems: 1 - items: - - const: core - - const: bus - - const: axi - - const: block - - const: timer - resets: maxItems: 5 @@ -63,6 +45,43 @@ properties: description: Specify the number of delay for tx sampling. $ref: /schemas/types.yaml#/definitions/uint8 +if: + properties: + compatible: + contains: + const: sophgo,sg2042-dwcmshc +then: + properties: + clocks: + items: + - description: core clock + - description: timer clock + - description: card clock + + clock-names: + items: + - const: core + - const: timer + - const: card +else: + properties: + clocks: + minItems: 1 + items: + - description: core clock + - description: bus clock for optional + - description: axi clock for rockchip specified + - description: block clock for rockchip specified + - description: timer clock for rockchip specified + + clock-names: + minItems: 1 + items: + - const: core + - const: bus + - const: axi + - const: block + - const: timer required: - compatible @@ -96,5 +115,15 @@ examples: #address-cells = <1>; #size-cells = <0>; }; - + - | + mmc@bb0000 { + compatible = "sophgo,sg2042-dwcmshc"; + reg = <0xcc000 0x1000>; + interrupts = <0 25 0x4>; + clocks = <&cru 17>, <&cru 18>, <&cru 19>; + clock-names = "core", "timer", "card"; + bus-width = <8>; + #address-cells = <1>; + #size-cells = <0>; + }; ...