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Thu, 01 Feb 2024 22:43:04 -0800 (PST) X-Forwarded-Encrypted: i=0; AJvYcCX4R0qDFeaJy982qi5eiCQC391aH5Ffpz/+ineKapBilqeevjYTAitfeFBMTjPa+gvB1EsA3lO9IDA5scj1w2ZHotBHONco0z8Hs3Tpciz7GZBBWBz+vWFxKDr6MEelmjZ9OZcKJlVkO/RBAUS8/D0RyHI1qO7LPjYkYuoWUeODjh8gBmVnCmBt8dG9TI8XWyZy2gr6Ys4Phg9He7ULmDT8+vuQ+gupoT8KNvptVFvaF1by7WIGL2bqb6nCTlx1vUxnJGXOWMvQIssiiVHqGDshYrvuiKmObj4u6NoD8euyrvd5pBY1oxdoPmXG7mR0jQWS2fd1FILhYg2vLkHFHIbPaaxDiDxfJMFEGvnF8jcJAftwPbUedkeElpvN79AHJUjhyB+3R/qDbdbGSH0bGzTMvxOapOjoyQ2auOiTsERY+Phdx2vuka3w0bcRwgGQwKtNYPyeNvW7QD9fNVlDf+l3jDr9JgkIcVzeycgqyS7ngBDE0CmSqWt3okOZT4R9LUjY/ySiJvd5m+0VaqA0+e0ymG2+MBTyq6gEUiKO26QmSeCaoQiKQD94SKZDbBeJrUXHqlwD4Rv6XJUh9yN8hhFkq5tdrZqr7x4Z4s9Qk9yv8XwabgxykqKxlN8OGuxH5DC2I58t9wHae2syY+Qnsrb+XkxkKK5C/klvjdflv4fAk2Q= Received: from localhost.localdomain ([122.8.183.87]) by smtp.gmail.com with ESMTPSA id q24-20020a05683022d800b006e1116e5169sm278807otc.7.2024.02.01.22.43.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Feb 2024 22:43:03 -0800 (PST) From: Chen Wang To: aou@eecs.berkeley.edu, chao.wei@sophgo.com, conor@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, palmer@dabbelt.com, paul.walmsley@sifive.com, richardcochran@gmail.com, robh+dt@kernel.org, sboyd@kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, haijiao.liu@sophgo.com, xiaoguang.xing@sophgo.com, guoren@kernel.org, jszhang@kernel.org, inochiama@outlook.com, samuel.holland@sifive.com Cc: Chen Wang Subject: [PATCH v9 5/5] riscv: dts: add clock generator for Sophgo SG2042 SoC Date: Fri, 2 Feb 2024 14:42:56 +0800 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240201_224306_884283_6FC1BC98 X-CRM114-Status: UNSURE ( 9.62 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Chen Wang Add clock generator node to device tree for SG2042, and enable clock for uart. Signed-off-by: Chen Wang --- .../boot/dts/sophgo/sg2042-milkv-pioneer.dts | 12 ++++++ arch/riscv/boot/dts/sophgo/sg2042.dtsi | 41 +++++++++++++++++++ 2 files changed, 53 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts index 49b4b9c2c101..80cb017974d8 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts +++ b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts @@ -14,6 +14,18 @@ chosen { }; }; +&cgi_main { + clock-frequency = <25000000>; +}; + +&cgi_dpll0 { + clock-frequency = <25000000>; +}; + +&cgi_dpll1 { + clock-frequency = <25000000>; +}; + &uart0 { status = "okay"; }; diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi index ead1cc35d88b..d83b6a01fbd9 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi @@ -5,6 +5,7 @@ /dts-v1/; #include +#include #include "sg2042-cpus.dtsi" @@ -18,12 +19,49 @@ aliases { serial0 = &uart0; }; + cgi_main: oscillator0 { + compatible = "fixed-clock"; + clock-output-names = "cgi_main"; + #clock-cells = <0>; + }; + + cgi_dpll0: oscillator1 { + compatible = "fixed-clock"; + clock-output-names = "cgi_dpll0"; + #clock-cells = <0>; + }; + + cgi_dpll1: oscillator2 { + compatible = "fixed-clock"; + clock-output-names = "cgi_dpll1"; + #clock-cells = <0>; + }; + soc: soc { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; + pllclk: clock-controller@70300100c0 { + compatible = "sophgo,sg2042-pll"; + reg = <0x70 0x300100c0 0x0 0x40>; + clocks = <&cgi_main>, <&cgi_dpll0>, <&cgi_dpll1>; + #clock-cells = <1>; + }; + + rpgate: clock-controller@7030010368 { + compatible = "sophgo,sg2042-rpgate"; + reg = <0x70 0x30010368 0x0 0x98>; + #clock-cells = <1>; + }; + + clkgen: clock-controller@7030012000 { + compatible = "sophgo,sg2042-clkgen"; + reg = <0x70 0x30012000 0x0 0x1000>; + #clock-cells = <1>; + }; + clint_mswi: interrupt-controller@7094000000 { compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi"; reg = <0x00000070 0x94000000 0x00000000 0x00004000>; @@ -333,6 +371,9 @@ uart0: serial@7040000000 { interrupt-parent = <&intc>; interrupts = <112 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <500000000>; + clocks = <&clkgen GATE_CLK_UART_500M>, + <&clkgen GATE_CLK_APB_UART>; + clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; status = "disabled";