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[84.72.105.84]) by smtp.gmail.com with ESMTPSA id r3sm814224lfc.131.2021.10.16.03.54.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 Oct 2021 03:54:17 -0700 (PDT) From: Nicolas Frattaroli To: Cc: Nicolas Frattaroli , Liam Girdwood , Mark Brown , Rob Herring , Heiko Stuebner , Jaroslav Kysela , Takashi Iwai , Philipp Zabel , linux-rockchip@lists.infradead.org, alsa-devel@alsa-project.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 0/4] Getting rid of the reset controller in i2s-tdm Date: Sat, 16 Oct 2021 12:53:49 +0200 Message-Id: <20211016105354.116513-1-frattaroli.nicolas@gmail.com> X-Mailer: git-send-email 2.33.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211016_035421_339346_7E9EF3D0 X-CRM114-Status: GOOD ( 18.37 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org Hello, after some discussion with Heiko on IRC, he has admitted to me that the rockchip,cru property, and its corresponding half a reset controller in the driver, is weighing heavily on his mind. The background is that if the lrck only uses one clock for both rx and tx direction, then according to the downstream driver, the rx and tx resets should be asserted at roughly the same time to keep things in sync. Since there is no existing kernel way of doing this, the driver would manually write to the CRU's registers to achieve this, violating abstractions. We've agreed that an atomic bulk reset API would be the best way to achieve what it does in a clean fashion. The details of such an API have yet to be worked out by me, but as it turns out, this is not a pressing need. During my investigation, I noticed that I can simply drop the synchronised reset for now and assert the two resets manually one after the other, and deassert them in the same manner. For the case I care about, which is audio playback, this seems to work just fine. Should someone actually find a case where this causes a problem, it should be fixed with an atomic bulk reset API. Patch 1 removes the direct CRU writing stuff from the i2s-tdm driver. Patch 2 drops the rockchip,cru property from the bindings; they have not yet been in a kernel release, so as far as I know, we can still change them with no regard for backwards compatibility. Patch 3 adds the rk356x i2s1 node without the rockchip,cru property. Patch 4 adds the analog audio output on Quartz64, included here for Heiko's convenience. Regards, Nicolas Frattaroli Nicolas Frattaroli (4): ASoC: rockchip: i2s-tdm: Strip out direct CRU use ASoC: dt-bindings: rockchip: i2s-tdm: Drop rockchip,cru property arm64: dts: rockchip: Add i2s1 on rk356x arm64: dts: rockchip: Add analog audio on Quartz64 .../bindings/sound/rockchip,i2s-tdm.yaml | 16 --- .../boot/dts/rockchip/rk3566-quartz64-a.dts | 31 ++++- arch/arm64/boot/dts/rockchip/rk356x.dtsi | 25 ++++ sound/soc/rockchip/rockchip_i2s_tdm.c | 126 +++--------------- 4 files changed, 76 insertions(+), 122 deletions(-)