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Sat, 05 Mar 2022 13:58:40 -0800 (PST) Received: from master-x64.sparksnet ([2601:153:980:85b1::10]) by smtp.gmail.com with ESMTPSA id h188-20020a376cc5000000b00648d7e2a36bsm4230067qkc.117.2022.03.05.13.58.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 05 Mar 2022 13:58:40 -0800 (PST) From: Peter Geis To: Cc: robin.murphy@arm.com, linux-rockchip@lists.infradead.org, Peter Geis , Jaehoon Chung , Ulf Hansson , Heiko Stuebner , linux-mmc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 0/2] fix dw-mmc-rockchip rk356x clock rates Date: Sat, 5 Mar 2022 16:58:33 -0500 Message-Id: <20220305215835.2210388-1-pgwipeout@gmail.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220305_135842_659567_F5D984F5 X-CRM114-Status: GOOD ( 18.16 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org cc: Jaehoon Chung cc: Ulf Hansson cc: Heiko Stuebner cc: linux-mmc@vger.kernel.org cc: linux-arm-kernel@lists.infradead.org cc: linux-rockchip@lists.infradead.org cc: linux-kernel@vger.kernel.org While lighting off support for the SoQuartz module, it was discoved the dw-mmc-rockchip driver has tremendous log spam when the cd-broken flag is enabled and no card is inserted. The SoQuart requires the cd-broken flag as the CM4 module pinout it follows has no card-detect pin. These errors occur during card initialization on all rk356x chips, but are amplified by cd-broken as the function is called multiple times each poll cycle. It was discovered the lowest possible clock rate the rk356x cru can provide for the ciu clock in the default configuration is 750khz. There is an internal clock divider that makes the final minimum clock 375khz. We could hardcode this, but it is possible it could change if the default clock configuration changes. To fix this, we must make two changes: First, the dw-mmc core needs to be updated to allow a host driver to save its requested minimum frequency. This is necessary as the mmc_host struct isn't available when the host drivers initialization code is called. The dw-mmc core can then apply the f_min later when the struct is available. Second, the dw-mmc-rockchip driver is extended to test the frequencies mmc core will use during card initialization. It finds the lowest supported frequency from the cru and saves it for later use by dw-mmc core. Changelog: v3: - add support in dw_mmc core for saving the minimum frequency (fixes setting f_min) - add test for the lowest supported frequency to avoid clamping configs that don't have an error v2: - change from muting the error to attempting to fix the underlying issue by setting f_min in driver initialization Peter Geis (2): mmc: host: dw_mmc: support setting f_min from host drivers mmc: host: dw-mmc-rockchip: fix handling invalid clock rates drivers/mmc/host/dw_mmc-rockchip.c | 27 +++++++++++++++++++++++---- drivers/mmc/host/dw_mmc.c | 7 ++++++- drivers/mmc/host/dw_mmc.h | 2 ++ 3 files changed, 31 insertions(+), 5 deletions(-)