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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: EtHvvILHIfUte7GgqzfIWALlyjAklnOgP9lIo/dN3PvcrWT4IM9kmgdRUd3qLDPHeUWjl3WVGaOaRg188cwi8jM1pJ7nPKRS+Cx6uzk4xya0ZKOAFUFv4WLLfmpZSxGUm/VnotyEncq3Ua0F4hI3bXQQk9YgFYPiFHuCoJBnt5nqFrzbf9oVP62IQGfgXzCBiYu42WgyFShhdqprglenfDujGDV7oWyQ1nssNN+HCnWrglYCgd9HLV0xYKUBWo0KiSR5Rr/wLksNpJaj2VXQrQ3vLYP+/c3ORq8aQVEezmQ21r2MEQQAOwzU6v/Ts0egiEtsRkD4dI486A3b4O4/wtN+ECovZfAgDasmYWB8i1gGJy6AIPythOM4wd8jS4qK/lpf5Z0n6BMOLTCTf5TBEk4BgzWf/Y7DSc+seK1lunldT4rAD1rAATF5DuaQf+IihEfnEn6gtLwWNPjBZcgISxCi6x+wiKixqB/I0PjXzE5Yir4cuy8kEvrYvE9j11ChCH/Rca92uPDNC4ZBPDnfhiNTQnys4yZTFco3hoIdV4zk65xwoJ1rmg1bah/NuEH9nEMzenSDSnWgW4bACcrMrcIrAZBAPPqbVPcbt9sxQ+axqfwj7vAihoraOiJrVMHrJ1+M+93xEI5l4no5lGfVJEdNUUhGjfUIFlmo5CUrNxMJb6SRDnVYi/DxOfQh0LqxdX10zexhC0JSNGWCvQG8tBVjMfOoH8qAACZfJzjdDb692V4x5Kmzt7c27CLeX/ADnD4YOoxTNWoPX3RpCq7pjKP9RxM57UZDTk3NQhXB6IVViIEhz7ky0fmE3iBcrFxHgOYdIv4UCHfDfu+0oUMbCDy7nHNaVemppEpoCeaSlj/zYqI7R0cy7t7bDrrr33jjuyVAyJKfOQFF6YF3zVaOX6PJV9S7BPqg7cZiO128e5CYOD6G5M90KkUUT0w3cK6eFtxSUEzu98/l6/Q9C2i2EetBzOgFsWiwICn2n2Y6ZhS6vM8erIKxM7hoFWDuP4qAvcjE8ukCxipzFUESBK7g3iTA7qttzsTn3cWD9fEQ94BHsSILqwlgaTT+xGMLf04K1gJBdOXyB7Lt+eYnJkJBcz4VYNYPANB5MCrhkxfWCM8H1U+ORW0dfYIpZ1C6S13Pgqh/5MxQdylJaPIclPX7RUGMA216pVO4/4B+4fYin8Pk4roTNaKAjNPGXZ0DH/T+9+CtcmfPUV8vYqjMr5vlbkqGRKExKTqNJCeLMvi+uaaUq3muSEEW3rR6S9h1Cg9TD1yutfbkZFl2IN3S2EjVQ4Tg3FX/Op8K0e9PKauqO1WcVxUbl+6oeYSVLrrCFbLzOQxzVfoAa80SRNHkH9ud+7BMUTl77sBGAT2eIp3BuMdkeQdf7ydW43tIaaZ79bL0prj7UX5tTUKFt6owe1Q4sP+l2BY1YlG5vxBkD9jVmIqH0O77NL2cVebiLPWwBvzmNJOhjUlFezAE5WTi+TjtAq3S9/iYnUY1iEPmVf1/oG5IUZZLanTbDl36Z+Btj9iHKFIh+kntO/E6GmX2YoXd+S5C0bzLVIEjCy5ACGuafVIsbk3wM7Aw3CshQ6BxSRjY X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 1b35a496-4181-439b-0d0c-08db6e9c4b64 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Jun 2023 19:02:56.3597 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: bnrPyhNONpiLvOpeXVchz3YP0B5OZmfteUyOUn5TrqWy64QKzxA2zcKekWiVs6Kn X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6051 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230616_120312_698234_8F2C7433 X-CRM114-Status: GOOD ( 14.97 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org What tegra-smmu does during tegra_smmu_set_platform_dma() is actually putting the iommu into identity mode. Move to the new core support for ARM_DMA_USE_IOMMU by defining ops->identity_domain. Signed-off-by: Jason Gunthorpe --- drivers/iommu/tegra-smmu.c | 37 ++++++++++++++++++++++++++++++++----- 1 file changed, 32 insertions(+), 5 deletions(-) diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c index 1cbf063ccf147a..f63f1d4f0bd10f 100644 --- a/drivers/iommu/tegra-smmu.c +++ b/drivers/iommu/tegra-smmu.c @@ -511,23 +511,39 @@ static int tegra_smmu_attach_dev(struct iommu_domain *domain, return err; } -static void tegra_smmu_set_platform_dma(struct device *dev) +static int tegra_smmu_identity_attach(struct iommu_domain *identity_domain, + struct device *dev) { struct iommu_domain *domain = iommu_get_domain_for_dev(dev); struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); - struct tegra_smmu_as *as = to_smmu_as(domain); - struct tegra_smmu *smmu = as->smmu; + struct tegra_smmu_as *as; + struct tegra_smmu *smmu; unsigned int index; if (!fwspec) - return; + return -ENODEV; + if (domain == identity_domain || !domain) + return 0; + + as = to_smmu_as(domain); + smmu = as->smmu; for (index = 0; index < fwspec->num_ids; index++) { tegra_smmu_disable(smmu, fwspec->ids[index], as->id); tegra_smmu_as_unprepare(smmu, as); } + return 0; } +static struct iommu_domain_ops tegra_smmu_identity_ops = { + .attach_dev = tegra_smmu_identity_attach, +}; + +static struct iommu_domain tegra_smmu_identity_domain = { + .type = IOMMU_DOMAIN_IDENTITY, + .ops = &tegra_smmu_identity_ops, +}; + static void tegra_smmu_set_pde(struct tegra_smmu_as *as, unsigned long iova, u32 value) { @@ -962,11 +978,22 @@ static int tegra_smmu_of_xlate(struct device *dev, return iommu_fwspec_add_ids(dev, &id, 1); } +static int tegra_smmu_def_domain_type(struct device *dev) +{ + /* + * FIXME: For now we want to run all translation in IDENTITY mode, due + * to some device quirks. Better would be to just quirk the troubled + * devices. + */ + return IOMMU_DOMAIN_IDENTITY; +} + static const struct iommu_ops tegra_smmu_ops = { + .identity_domain = &tegra_smmu_identity_domain, + .def_domain_type = &tegra_smmu_def_domain_type, .domain_alloc = tegra_smmu_domain_alloc, .probe_device = tegra_smmu_probe_device, .device_group = tegra_smmu_device_group, - .set_platform_dma_ops = tegra_smmu_set_platform_dma, .of_xlate = tegra_smmu_of_xlate, .pgsize_bitmap = SZ_4K, .default_domain_ops = &(const struct iommu_domain_ops) {