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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: KRA4dkN6SFbhY/PhxcCiHyKWQpKjz2jW7UNjCB3po56EaZgKgUO4nOd4GBIGgMv997a2WVc7I/KyP+FjBxMMP1RKA96zebLhPb79pSTWzFJgim+3f/kWvmk7NyDjLc1fwuXxhZkpCXPN9fE4ItGW4/2xKnc6E2I0bfwJXHLcvTn0ZJ9rLwJfjP9OWY90I+eYrhI1XIYFEWVqpuOX1cVQJxKTejZyayApNzZ6f5mP8qvLHfqvFflKxYcQaAznvMKIanaozC5PEbjJU1xWn1fYpQ6IbRnI2TTON7P/HPH8OsnZNBS7nACHLuP6g/c/+bpeEd6ypnTlgnRRdbC4rZ8TrYNYwDaFYqPcI0bhR7R0ySK3TiFJj0+Id4eAJUTqps1iaM/77/uA18uS/U/VM+2bIu6Ytz6oQPEYS22J0u+EAusKY80fihGUB3rE65iAm3Ug10bh1KVJkFQv3zNJ4YMB7QjmXrPsr+cowGDa6EWTKpNmSrFWfG/3+E61wlgb0eKZTnpBbgV8F7HgR0FJSNUUvWuD24oE2ehSQEQtw0lhbnQZ8GXhpq87/l37z3qiigNRa+nL8FfFcGs+Xzp86ElcrvrtKWtt2dTAnOnF8iZ4/fX/Bdic0qiWw++dpp3+9VGANI2BLULXhI6iN02irQqjcE5doFZ/VBq9yS+q8Rohh7kMQb6woBrP+/+mwopsCDzS0/3ci8JEIBlIHGc6J/r85ZArEgAyCooHbuyURPd5NvewZfL4mkcE023W7Ft8XIaR1xw92o5wcSpi1dbBPBsQ+fhIyxqBH0UzOarXN5V2bOVSF8eYQk/aKWY9TMYUPgKaVlX/OD8DbS5ce16ppkxSCwhHbpLQEu6fgASdbp3DMgWEMgDZo5FLS9++lHqQjlXl0toPBjZHRxtnQBKV0uy6j5iaPjbOW/fZU3CQdlreFaRXADSH0vuAiiZoRPgAhsh7HpGYMrRaRgjKx1pBN+LuCrDkeyWP0rYAkrvPydmGsoV7a0pgl7//kcSYq6LkMKw9s0SOw3791wFcHIzgjmGEsIkpB0bsUkC0Hgm5dDpttn3Ej0gvSCF1tGH76dcrJekyXh5T+veeAl4R9mhHj6Py8RLb1yn6+6ofymXu4AVL8acUqVr592b/3WpeOsmkXPQSTa2ynPQ+npsCYOXuqXRWuZ3mo/fIwsO0MJFkAvhdU3YytMg2NA1iPtPYqWxuoaw31tumy5bUlK57wRI3dX2cugGcn/GJSZEwx6itzp0B5VhQAfz0tMEXVie7r6rUh7wwTnnlglihK9BLrhweyM9EqVATVMhvI0n1wf/Nu4LywwAB3rq0ZpynXDAExiUO0EuhIgD+BP22OZtLUwHYbj8kSqQzDtCHCcCW8Kkb9/uJxxKmwF7y9uLO+1GJWoUX05gE/FvLXGeXJuI/UkUGYSAk69eeOL2KM8Nwl8xDNmVuAyB6KwWZXc83LHU8D07SEWXxzo+KVm9JeiwrblInoDkOit2jf+d5D+1/8wqYMyhoWXsx+ke46VJ+oPnVAf7kAy8Z1zPQgRW8Tq8ASVpzYsz1zUrkV3dNx0ECcVcb+sHxpCUiE3Wr9jpKf5puxlPOQraK X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: f9d28118-7208-4916-eb90-08dbb45f80e5 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Sep 2023 13:44:08.2909 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: nvBp9wR+2KK0icFR0MLheJ1G1tbpT+otaGTmZ30lcId6magrsCIXei2DvGQ4IfYw X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB7848 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230913_064415_168620_5FB1DE72 X-CRM114-Status: GOOD ( 15.21 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org What tegra-smmu does during tegra_smmu_set_platform_dma() is actually putting the iommu into identity mode. Move to the new core support for ARM_DMA_USE_IOMMU by defining ops->identity_domain. Reviewed-by: Lu Baolu Reviewed-by: Jerry Snitselaar Signed-off-by: Jason Gunthorpe --- drivers/iommu/tegra-smmu.c | 37 ++++++++++++++++++++++++++++++++----- 1 file changed, 32 insertions(+), 5 deletions(-) diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c index e445f80d02263b..80481e1ba561b8 100644 --- a/drivers/iommu/tegra-smmu.c +++ b/drivers/iommu/tegra-smmu.c @@ -511,23 +511,39 @@ static int tegra_smmu_attach_dev(struct iommu_domain *domain, return err; } -static void tegra_smmu_set_platform_dma(struct device *dev) +static int tegra_smmu_identity_attach(struct iommu_domain *identity_domain, + struct device *dev) { struct iommu_domain *domain = iommu_get_domain_for_dev(dev); struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); - struct tegra_smmu_as *as = to_smmu_as(domain); - struct tegra_smmu *smmu = as->smmu; + struct tegra_smmu_as *as; + struct tegra_smmu *smmu; unsigned int index; if (!fwspec) - return; + return -ENODEV; + if (domain == identity_domain || !domain) + return 0; + + as = to_smmu_as(domain); + smmu = as->smmu; for (index = 0; index < fwspec->num_ids; index++) { tegra_smmu_disable(smmu, fwspec->ids[index], as->id); tegra_smmu_as_unprepare(smmu, as); } + return 0; } +static struct iommu_domain_ops tegra_smmu_identity_ops = { + .attach_dev = tegra_smmu_identity_attach, +}; + +static struct iommu_domain tegra_smmu_identity_domain = { + .type = IOMMU_DOMAIN_IDENTITY, + .ops = &tegra_smmu_identity_ops, +}; + static void tegra_smmu_set_pde(struct tegra_smmu_as *as, unsigned long iova, u32 value) { @@ -962,11 +978,22 @@ static int tegra_smmu_of_xlate(struct device *dev, return iommu_fwspec_add_ids(dev, &id, 1); } +static int tegra_smmu_def_domain_type(struct device *dev) +{ + /* + * FIXME: For now we want to run all translation in IDENTITY mode, due + * to some device quirks. Better would be to just quirk the troubled + * devices. + */ + return IOMMU_DOMAIN_IDENTITY; +} + static const struct iommu_ops tegra_smmu_ops = { + .identity_domain = &tegra_smmu_identity_domain, + .def_domain_type = &tegra_smmu_def_domain_type, .domain_alloc = tegra_smmu_domain_alloc, .probe_device = tegra_smmu_probe_device, .device_group = tegra_smmu_device_group, - .set_platform_dma_ops = tegra_smmu_set_platform_dma, .of_xlate = tegra_smmu_of_xlate, .pgsize_bitmap = SZ_4K, .default_domain_ops = &(const struct iommu_domain_ops) {