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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: pnS2x/jW2hl5ekb4rLHYAEha9CBDQlyBWqx0V2WtlGr/nDVqS/juNcahf7qm3ImLO9MKRNzzByN3MVbY9Y7RdeNVjJ6i9kGP+7XZhg8iP7mND+6pQiVoU7pj0kQKXwcfLm4YjjgrQM8bs81Q+xGG7W2ZaOXPFV2pkwXmm035StmYJunaT6J5QMUzsqbaMhPIpzoBexJVG53xaXXEeef90LrKk7IRQthMgKczw1dHEwo2Zp+Hn/e8+XovnPRHnHF+nDvvEXiIJ+9CKaFkRyVGwAzsN2z9bSEqPcP0wjnjbbwHxc8fnUaB2ToU3SZquL3u+fOjgYxk86Mm7iAbRL705PosSCcH9fhSKDWqjWB5W9FsLbfaZD0sZuI/0RDNG4AFWyr1rrDDTe3e7IMjoqP3/mM3F59WTpUtTm+xjG5khVXZO7Xoby/29ySIN92+whziudke+4avue+o2cAnKBxRwkUycEeH18N5zp4JNt7Ih75JMTKnW6Osd7nCeEsdSnbxTdKUCV0aH7IerplL7mLFKLckqfO03DYyNM0z0A6313MRXSwBQ95nhgwyK0rxpIe5COLw01Hrxi3Z/gyCxFeYiz7O6+X3762HqNnlj9odsKLCHkKEkQx1o/2reF2aTSUsCo6qQ5/G69T7h4M02cc9mWhW0s7PDMtyVed9UF1PPqgEq0wit3z3fn3zTAaAT6/w6XEO2xLL1cMcULIYDs67dYRQtOXoBZaNsdmpp29jFz+vKLJvxLWnwkgO08Sqfx94QVn3QTXg0Pa4rN0Q3McFeokCBSWikVtAK213yfvfV4xZN2vx7Q3GfIQ53io1T7J8IU9zjfQUO8F45JEDjNC/oAnTXD2/HiZEo8OwQ58UVIOstUPziD6/mW5I4JBgSViZ2kNnuop/8AjEvBZxCGJhIyTY3B0dwwsM09+PcegZ03B1+CQJflAOHpankaLXsvdGvTSOPHhlThfcjh//1gTXW3afyiwsXSW1UIL5C5KpQVArKdMW2BvODRrg9BM0QtNb/3Q/iFjtga9rak6xzRHBXkaqPCXRy1ucjosnEEsUDu0yQuxANGyd+ip3X//bceB78uKN8coreTvaB4S0wKmxqN+11Z8pKZc838pMKzEdyqHjy/hhJCV+jG/1pG4jo3vnlMFaVFtdAJZDkIuRrWHJbC1H9AOQmwpGCUWTy6Mm2GuEDi+y+S6R8bd/SmYsQ4UV5Il8JFl5XWkRMOkln9xPPZyE2Bp8xNMGQjKS+6o98QkLNsKkzd2CzvOwXFCYt+WV7izn48Bvlbki+iqdQMFAFcwa6GwyYimBEVFvP0rLPqcq/CZejAj/u4laJItmDaPK4piCP6ecCufIYi3J+yMw8AMKf5Wl6anFT778q96vDlDUk7mC0LWyVhf4ALQxDEoHTHDXa3n/wvKhB0uquzu5gyo0/wY478wPGLKk8cUzGNOENm2wHmdPox/OnGsT8XZ6fxnKzogcV8DK07LsAyYoE80Bu6Iclnz7XEo4+tNiI7jpTUp+JN9LHqe9gDxFj8aX4Lwq81ca//hebb8SEvoTjJ7TlGHgYYB4BVyNR2uX4PK/5uxaddc/6/ydBCbxl7Ac X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 6d97404f-e116-4255-fcae-08db69239626 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jun 2023 19:56:17.0515 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 0uESICC2lODOvu3vukrqYvrdYTOmOuTPPCeOUIx6ojdfXdb8mu1ykAtJHAP/cq00 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5264 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230609_125628_037351_B15CFB74 X-CRM114-Status: GOOD ( 14.16 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org What omap does during omap_iommu_set_platform_dma() is actually putting the iommu into identity mode. Move to the new core support for ARM_DMA_USE_IOMMU by defining ops->identity_domain. This driver does not support IOMMU_DOMAIN_DMA, however it cannot be compiled on ARM64 either. Most likely it is fine to support dma-iommu.c Signed-off-by: Jason Gunthorpe --- drivers/iommu/omap-iommu.c | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/omap-iommu.c b/drivers/iommu/omap-iommu.c index 537e402f9bba97..34340ef15241bc 100644 --- a/drivers/iommu/omap-iommu.c +++ b/drivers/iommu/omap-iommu.c @@ -1555,16 +1555,31 @@ static void _omap_iommu_detach_dev(struct omap_iommu_domain *omap_domain, omap_domain->dev = NULL; } -static void omap_iommu_set_platform_dma(struct device *dev) +static int omap_iommu_identity_attach(struct iommu_domain *identity_domain, + struct device *dev) { struct iommu_domain *domain = iommu_get_domain_for_dev(dev); - struct omap_iommu_domain *omap_domain = to_omap_domain(domain); + struct omap_iommu_domain *omap_domain; + if (domain == identity_domain || !domain) + return 0; + + omap_domain = to_omap_domain(domain); spin_lock(&omap_domain->lock); _omap_iommu_detach_dev(omap_domain, dev); spin_unlock(&omap_domain->lock); + return 0; } +static struct iommu_domain_ops omap_iommu_identity_ops = { + .attach_dev = omap_iommu_identity_attach, +}; + +static struct iommu_domain omap_iommu_identity_domain = { + .type = IOMMU_DOMAIN_IDENTITY, + .ops = &omap_iommu_identity_ops, +}; + static struct iommu_domain *omap_iommu_domain_alloc(unsigned type) { struct omap_iommu_domain *omap_domain; @@ -1732,11 +1747,11 @@ static struct iommu_group *omap_iommu_device_group(struct device *dev) } static const struct iommu_ops omap_iommu_ops = { + .identity_domain = &omap_iommu_identity_domain, .domain_alloc = omap_iommu_domain_alloc, .probe_device = omap_iommu_probe_device, .release_device = omap_iommu_release_device, .device_group = omap_iommu_device_group, - .set_platform_dma_ops = omap_iommu_set_platform_dma, .pgsize_bitmap = OMAP_IOMMU_PGSIZES, .default_domain_ops = &(const struct iommu_domain_ops) { .attach_dev = omap_iommu_attach_dev,