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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: v02JbY16jTCFtltKjqx6yHgbTZKQGxkUbaFt3DZXk6V+5qgIsDje6CD+tmUV4q6YD8C64SGeUEystgChlqJ8v5gTnGc3aNY10Ciroer49arShxPiXpeofrXLLlbFQu69BWSEgcMtiS+Z/FWn/VLBoDHMO7ovMIZAlbr9S8CY8oD+4Z9fCQLPl8aimVYM5OZ2QJRguqKSPz33nnGT1sSldooFJP78+jALi0any3DhaSqyzQ5c71WDfodFdPN77Wpayl4LNsgRI3dWVi0OLQpxIcN6fB5yHkKbeANwNKX429Tb3adSdQQ5DEQhy2rwDwSQD5cJqs4pcUVkRptKETsF/w81PVItW1q5fpmV0//uPEf5psgz/drcde24QctD7/JVM3G3ye7TVCBSFIs0Uwg55qjHBnCz+vp9AqnlyOq5FdkNU0jTY3RH8IJaMmGMe4L45fYxTpE69h9u6ifTi0qYjDH0HzY8RbU8w9J4Zw+QQfk2ytKP5r2b3HWQl0BeQSkeULsemNw2scaPpE8pqI5dc7rqBosMMfMy1DHdiSQxUTOjVCt73qTirQD2yQb9Ea4njSPq+l2uStMsOug49PY64S/WvBGOMMfY9ZixhYwla9h0HbdzJ/Hpdi01hp/gtB8EZX0/A9fJcuCKg2Ld8eCJqjABP78Q/OapnAl9JURLiMuP4uTdJCzN8QJzMwOUO4c23F+xcKj469jjoPEALKQ27ZTNrQRQWzcdYtSJUn3pQe01VeP3Kqq7S5QMijt4oCgivsYix/lR0Dtba/kFwH7o1OT1W2bMTUVd10nU1avORE3XXg8r6XYmO/sKss++pNrQlrQTekaluXT+AACkCwIUugbN5hNCygGlGnXhhgPHCEBN5GstTZongcwrNfJAuTzQ0ZGaTmzVD3SXxEVszQJKv/fl+sNvR1SS3TsTyL+JR2wnl5ln4P8PcLOTOpDjdRKQZA6ERTBJmSBqc5edt0WGAiR67AjN8PU1xGLq5C6UKbYDPETzv/AlWJnRHHifuIHkNdIAqP/1whBk70VD1r75B2rxS77BVIxScnw1QCnS8TaOP77bmQlx5r8JTnbxs2ph3z9nDhBOdxYq4pj+7cUDofCP0Xg9xemPKN1K0qAo54/1CcRoHwIG2YwvwJpAbIy4zcuHVBhj3OKLRQ6F/wdQkk8f4BPAOExhoADAO/oYDnHlCuAB3nyr01iVrkD38MhVL0Z0yD3hlPgAMxZhR51yiVWlp/VvAoWi6PlWOPpCZZu9Zh1usKyRf72qsx8pRouybQ216Wv7ETVvcIlZ4l9pV2F5cDB82+S1rZ/NIowZzA5+RCkNkE5t3iF2+VHHgSRiJXQYwY74Jv0GhQ399yHOrB7lAhKHAwM/qqCg3OVHI7DM2ynl6reBUujArwfHrsnY/o2vmQ6e/d0rSSRqxGYs2Hy0MaJKW9J+DYqNgPfYBTaPqf0HjcyI7Wi8qhDNJ0UNNFKJr+T+E5sAUGMapWYl4obuX2Bvlxnc2JqGN046OWnK3mX++ILhvXYE6xMSlTcfEI3eru/WWyqtIjE6WkN+G00CnYZixDRhAgcKXhLQRYiKZA5n6EhvXlJWmVU3xFrn X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: e15153d6-da58-4770-3404-08db6e9c4c38 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Jun 2023 19:02:57.7178 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: VSipxwvi8jAscsPkljHGjmlz6rYZAdnvitxnyl8+NhFFXY22uHdPo8rjPrWBq7/5 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB5912 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230616_120316_873608_D6008217 X-CRM114-Status: GOOD ( 14.18 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org What omap does during omap_iommu_set_platform_dma() is actually putting the iommu into identity mode. Move to the new core support for ARM_DMA_USE_IOMMU by defining ops->identity_domain. This driver does not support IOMMU_DOMAIN_DMA, however it cannot be compiled on ARM64 either. Most likely it is fine to support dma-iommu.c Signed-off-by: Jason Gunthorpe --- drivers/iommu/omap-iommu.c | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/omap-iommu.c b/drivers/iommu/omap-iommu.c index 537e402f9bba97..34340ef15241bc 100644 --- a/drivers/iommu/omap-iommu.c +++ b/drivers/iommu/omap-iommu.c @@ -1555,16 +1555,31 @@ static void _omap_iommu_detach_dev(struct omap_iommu_domain *omap_domain, omap_domain->dev = NULL; } -static void omap_iommu_set_platform_dma(struct device *dev) +static int omap_iommu_identity_attach(struct iommu_domain *identity_domain, + struct device *dev) { struct iommu_domain *domain = iommu_get_domain_for_dev(dev); - struct omap_iommu_domain *omap_domain = to_omap_domain(domain); + struct omap_iommu_domain *omap_domain; + if (domain == identity_domain || !domain) + return 0; + + omap_domain = to_omap_domain(domain); spin_lock(&omap_domain->lock); _omap_iommu_detach_dev(omap_domain, dev); spin_unlock(&omap_domain->lock); + return 0; } +static struct iommu_domain_ops omap_iommu_identity_ops = { + .attach_dev = omap_iommu_identity_attach, +}; + +static struct iommu_domain omap_iommu_identity_domain = { + .type = IOMMU_DOMAIN_IDENTITY, + .ops = &omap_iommu_identity_ops, +}; + static struct iommu_domain *omap_iommu_domain_alloc(unsigned type) { struct omap_iommu_domain *omap_domain; @@ -1732,11 +1747,11 @@ static struct iommu_group *omap_iommu_device_group(struct device *dev) } static const struct iommu_ops omap_iommu_ops = { + .identity_domain = &omap_iommu_identity_domain, .domain_alloc = omap_iommu_domain_alloc, .probe_device = omap_iommu_probe_device, .release_device = omap_iommu_release_device, .device_group = omap_iommu_device_group, - .set_platform_dma_ops = omap_iommu_set_platform_dma, .pgsize_bitmap = OMAP_IOMMU_PGSIZES, .default_domain_ops = &(const struct iommu_domain_ops) { .attach_dev = omap_iommu_attach_dev,