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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: HOAjmxUJTNdaFvNbJJMLN5i3lplfQaOM7vpVtc2nbXbTBB4de93AztsoTKL6wjuaSZvFt0hOSG62MsHgszDgpiO1aOSjvar9Asz8n7URdMzXJNML6o6GTLXs0TeEI49APY/PVS8tIDcwEYuwu1jUuNhtiiWAr34KpX6STZnw9uvxAlxALBnJLv0sWR6i89JS7NKP3jKnjceyKg38zaBYuuyYa/pm2tazyCPhmqswJDB72+jh9k/ZTsskLFkFgIyhZDbimupB7ebv5wnkJh/wSFjo9CALL8xg14V3mPNtgHg6e/16X5v4updUmshI6Z2bxAUC4K0k6BqzIMVxcP/8HbwSXkMfKxC9MjrGDOh7T1EDUaw5gUT/0KRxOrg0GhuMhimsLxczOxwCUJ9NbKTSRdghLkRPYUTI3B8uyqBi/EtnWiHsKh0Z4d4IVY0UG8UbGCCStjMR3jSoa3RzbA35FiuNGbbdqt7H16w8Ihw73KURl/jjisUsMrDf3XI6zvhVu0L3yDkhmVJgpepJ50njKjjPP03gfD58P66ZBOasYkpNuvh+tuSXexkcd2iBUDA8+ayruPRud4EfWLWbdGj8QY2jnfRGii+cAZUvpUvoJh/8CUmKmApfWtmSwV6PKXl/R+wO1Fe9NqzQs63/3vAfGesgicvOAsgl7oElyzjChCIOyY3XVo6CCLf1GdpFNrsMkO3/G/VcLcTZBtUaYQdKWfqUjXaz0uGYzXl2VJrbduT/lFbEavlt6Vv5LNpdq5aE2v5k1I0v3KSc2mgdz2lKxTJLXEqpSkjFSQhtIUhYXNtkWUP+WB+te9WcvU4Ztepz3VU66cx8Pf80HfNDsS+IYg5h7zLPlrX6UFets8RJLOoJKDi9qSartWRiidk/EQnaYsqnDNPBiqeWD/XtrXoLaLq+s1moGr54Mpv2ugGOILrKNh4mDr2gz7lqJRO9LWJXg1crj8c96ILT0rMW2Gxjgk71ww+P1v2e5ga7Vb9lSR1uYxWzfPj8/DuxqKlYLladKwGHCe5L9Ib/uSV8OwS8ffp3ZUkHfT92aS6+Bwo8a6ixpxUCG9jw+Muw80CCT4VC7nRMzQNbO14+Ook2PRa+oGMAEtbnhC8urPOFXEonxIAIrnMMxBcNyYiVBbJyxRsdRXleioQG39+fl8gFf+Zdilrb78QOr1Fp1+kbZZLwdwlZVDDn7vQkPy52K97x8TrCm5ZNemR5EB8QcF/I1AzoYopOz5iNZKpSjog9oyKkd16VKDCHfifXXn1mcorWdlNH/8kBqGUk5dl7bHqQOq4TwSQxrQJ6YBgAd7HP+ZAi6hGaLGWT5fNQ6EqORgpThykAIartoshvoBAp1w3uHroeyqb9VV4aOgoh4z9IOAvEHqSl2g2XCu47nRVzKWP2yqKU+rbINk9XiwfL+QcBP3IuwT3UxyUzuaIr/EoM5tTbnMYg5N4MHItqFeydkySu9FC086NJuhHbwEDFBjowHnNwRMkv7J6GhoW2WMgqGrze7Nn1CAILikXpj/E6UtnrrCvun0QRp0/v6WUgAk7MTw8v/+LUxjPSC/9x0alDITCTnW0uYeIxERPT1OySr0CTRfOC X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: d0c8e12d-4e45-48ba-3a35-08db8c6a8898 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Jul 2023 17:22:19.0520 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: mQIed9KYYg3yklCzTIbCPGqU3zR/VH58nhoma018CNLIAj+ERsYxGojuVphyMpr1 X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB5252 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230724_102238_099356_810D032A X-CRM114-Status: GOOD ( 14.88 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org What msm does during omap_iommu_set_platform_dma() is actually putting the iommu into identity mode. Move to the new core support for ARM_DMA_USE_IOMMU by defining ops->identity_domain. This driver does not support IOMMU_DOMAIN_DMA, however it cannot be compiled on ARM64 either. Most likely it is fine to support dma-iommu.c Signed-off-by: Jason Gunthorpe --- drivers/iommu/msm_iommu.c | 23 +++++++++++++++++++---- 1 file changed, 19 insertions(+), 4 deletions(-) diff --git a/drivers/iommu/msm_iommu.c b/drivers/iommu/msm_iommu.c index 79d89bad5132b7..26ed81cfeee897 100644 --- a/drivers/iommu/msm_iommu.c +++ b/drivers/iommu/msm_iommu.c @@ -443,15 +443,20 @@ static int msm_iommu_attach_dev(struct iommu_domain *domain, struct device *dev) return ret; } -static void msm_iommu_set_platform_dma(struct device *dev) +static int msm_iommu_identity_attach(struct iommu_domain *identity_domain, + struct device *dev) { struct iommu_domain *domain = iommu_get_domain_for_dev(dev); - struct msm_priv *priv = to_msm_priv(domain); + struct msm_priv *priv; unsigned long flags; struct msm_iommu_dev *iommu; struct msm_iommu_ctx_dev *master; - int ret; + int ret = 0; + if (domain == identity_domain || !domain) + return 0; + + priv = to_msm_priv(domain); free_io_pgtable_ops(priv->iop); spin_lock_irqsave(&msm_iommu_lock, flags); @@ -468,8 +473,18 @@ static void msm_iommu_set_platform_dma(struct device *dev) } fail: spin_unlock_irqrestore(&msm_iommu_lock, flags); + return ret; } +static struct iommu_domain_ops msm_iommu_identity_ops = { + .attach_dev = msm_iommu_identity_attach, +}; + +static struct iommu_domain msm_iommu_identity_domain = { + .type = IOMMU_DOMAIN_IDENTITY, + .ops = &msm_iommu_identity_ops, +}; + static int msm_iommu_map(struct iommu_domain *domain, unsigned long iova, phys_addr_t pa, size_t pgsize, size_t pgcount, int prot, gfp_t gfp, size_t *mapped) @@ -675,10 +690,10 @@ irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id) } static struct iommu_ops msm_iommu_ops = { + .identity_domain = &msm_iommu_identity_domain, .domain_alloc = msm_iommu_domain_alloc, .probe_device = msm_iommu_probe_device, .device_group = generic_device_group, - .set_platform_dma_ops = msm_iommu_set_platform_dma, .pgsize_bitmap = MSM_IOMMU_PGSIZES, .of_xlate = qcom_iommu_of_xlate, .default_domain_ops = &(const struct iommu_domain_ops) {