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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: F1X2tmawWvei+c32esVYoFS/4e2F5mBnMkbOK8rcFqkHd5l8XhIbGfQVZNDhdxgPZfpWp5ZZVqTHnTRIVZiWtkxqnXzL+m7GV5AnhbgmW7qLu06pkKP0ewRwzNfVA9Ihh4HzEh1BnyANQ+xGI313mI92gOygSkYwRWypgJxpEcthd9phiHsbLYgVfqb7fuvhqLuCfJRdpDDGc7L0N6prKMwQ0BIwyYTSMlvzzBBDB7ZKQhKTPOXpcELE/4C8n18Pp8PBjqpsLwXD8mG6UeKPY6f47j+5+nfTAGu7PIhuKdhaMQiPLjeuTPA2bRsBx8V7JwWhkwIbaAQAvlA5GwnA07FsUTJxOsoEwb4lEEh+W+7S1ihw4N7XFu8JNklejALlaoOEXZaeBLCXMn8f1HP/+fOrp4/djUpC/WOzH0zEFga0eOyfD6YgbQuUOsz2h2q1Nnu6xkd7dR3OR5WVQlRbL+Y9KX3fhmUbSLgxnrc4DbnfOPr2cWgtsGb+EevKdy/7Oh2a8VYyqtbttsOqU6LYLufsv7taIeceUtOap0HM9xh8S0aWQshRowqOK1cj7m266Ud30YW3Pql2Posd1ZaM3+mFErwODFUXEpX/dyfefBSmOUgA1VmS4OlLcM90csKNY47WrT4vA/JOY055O22iYTP3E4H3vK36QWjtT3da8u9imMh/sOOMh8hwHNEFnPCj/JgXi7UbdsqGO2BOeapPZs4sR242gsu6v2y3O4RTDFcoqu58s8yh84dXC2K9U24zM1siWMJ3EqhUpSCnhmo3xcj/S1jxUoDvZcei3O7I2Bp00wZzTBN9KVQeliyjvTMxX0pWqnIHPxFN+6AWPTbS+xUtjEw7KiG5cH8Q1Pk5DQbCeVVN5pNYjOni6QcKWHvFwjFA0zz82JuyzGZTT7oPI0W+7nV4izxAfNOCRVUTYlWpcp13nmgUoVDprSiYgLALuJnPU5xE8TN1Rgbgstq49kGG9yXX63mZ0LSQZ6+si9Zz0q0MnwwWz4sqSIQ1sd0Fv149e5yu4X0/pbBgG9uQh98n4XbD3rygD6nI2I+WYjy1jwkHfEbsXl1HP1m8lOZJmY8AKnZNQfBoQhqJyWCXXb9pPGFYFaQwtaRHuu9wwARP1TznX9kG9bgKDRKaToaOaW/CPZBE2CePYa0F9yIawwug+phXdGuPbmBvDHc5bB08esF3jzpvRGgClCeoWgIHm8/mfuG2dKJcfZQDodnbWbRG9HIYZWNRFfbCRio/9e2EnepOfqTGVOkFgjfH4rKmo6b/tn0rh8jI96/DhmkxjE1ARVj/3Bj3sHVLQW7Glk5TCDfb8rBGWjJF84mbXQWq/Vh5UE5DCiS2U07O3zUYv2q6h4Nx/mqIIxIL8O9HpEUvFvl7KGEiHmtr54KyFa8W5PcCjOTSjwXopMME9ElQEKyWGefonxpEArrc0nboXkyjt1Kvt3Q2BCZhrf+yzxH3lqjE2cD/F98XK/pt2C1bts73Nfc5dtgoXosL5monKaqsfsUwOrwL+pbu5L6C88NPqJyb+Rcou1WzdxyMb8RHDxquf8PaWSOQgweO2URZpjB5u26mTxhppsaSBHan/J+6 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: f9c2988f-a516-4321-d22c-08db93b5bc3e X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Aug 2023 00:08:16.2672 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Z0qxX+iRdVyVjrxA6v/2RAzCT4tAYguTdVZfkmM24blHmpJ2LXycNlmWm6KyRUU3 X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB5809 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230802_170843_643258_66E4FC39 X-CRM114-Status: GOOD ( 15.23 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org What msm does during msm_iommu_set_platform_dma() is actually putting the iommu into identity mode. Move to the new core support for ARM_DMA_USE_IOMMU by defining ops->identity_domain. This driver does not support IOMMU_DOMAIN_DMA, however it cannot be compiled on ARM64 either. Most likely it is fine to support dma-iommu.c Signed-off-by: Jason Gunthorpe Reviewed-by: Lu Baolu --- drivers/iommu/msm_iommu.c | 23 +++++++++++++++++++---- 1 file changed, 19 insertions(+), 4 deletions(-) diff --git a/drivers/iommu/msm_iommu.c b/drivers/iommu/msm_iommu.c index 79d89bad5132b7..26ed81cfeee897 100644 --- a/drivers/iommu/msm_iommu.c +++ b/drivers/iommu/msm_iommu.c @@ -443,15 +443,20 @@ static int msm_iommu_attach_dev(struct iommu_domain *domain, struct device *dev) return ret; } -static void msm_iommu_set_platform_dma(struct device *dev) +static int msm_iommu_identity_attach(struct iommu_domain *identity_domain, + struct device *dev) { struct iommu_domain *domain = iommu_get_domain_for_dev(dev); - struct msm_priv *priv = to_msm_priv(domain); + struct msm_priv *priv; unsigned long flags; struct msm_iommu_dev *iommu; struct msm_iommu_ctx_dev *master; - int ret; + int ret = 0; + if (domain == identity_domain || !domain) + return 0; + + priv = to_msm_priv(domain); free_io_pgtable_ops(priv->iop); spin_lock_irqsave(&msm_iommu_lock, flags); @@ -468,8 +473,18 @@ static void msm_iommu_set_platform_dma(struct device *dev) } fail: spin_unlock_irqrestore(&msm_iommu_lock, flags); + return ret; } +static struct iommu_domain_ops msm_iommu_identity_ops = { + .attach_dev = msm_iommu_identity_attach, +}; + +static struct iommu_domain msm_iommu_identity_domain = { + .type = IOMMU_DOMAIN_IDENTITY, + .ops = &msm_iommu_identity_ops, +}; + static int msm_iommu_map(struct iommu_domain *domain, unsigned long iova, phys_addr_t pa, size_t pgsize, size_t pgcount, int prot, gfp_t gfp, size_t *mapped) @@ -675,10 +690,10 @@ irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id) } static struct iommu_ops msm_iommu_ops = { + .identity_domain = &msm_iommu_identity_domain, .domain_alloc = msm_iommu_domain_alloc, .probe_device = msm_iommu_probe_device, .device_group = generic_device_group, - .set_platform_dma_ops = msm_iommu_set_platform_dma, .pgsize_bitmap = MSM_IOMMU_PGSIZES, .of_xlate = qcom_iommu_of_xlate, .default_domain_ops = &(const struct iommu_domain_ops) {