From patchwork Wed Sep 10 18:46:53 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Heiko Stuebner X-Patchwork-Id: 4879721 Return-Path: X-Original-To: patchwork-linux-rockchip@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 466ED9F390 for ; Wed, 10 Sep 2014 18:46:04 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 2A5112016C for ; Wed, 10 Sep 2014 18:46:03 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 06E4520142 for ; Wed, 10 Sep 2014 18:46:02 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XRmu1-0007Em-NF; Wed, 10 Sep 2014 18:46:01 +0000 Received: from gloria.sntech.de ([95.129.55.99]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1XRmt8-0005aM-VQ; Wed, 10 Sep 2014 18:45:09 +0000 Received: from ip9234458b.dynamic.kabel-deutschland.de ([146.52.69.139] helo=diego.lan) by gloria.sntech.de with esmtpsa (TLS1.1:RSA_AES_128_CBC_SHA1:128) (Exim 4.80) (envelope-from ) id 1XRmsn-0004A8-2t; Wed, 10 Sep 2014 20:44:45 +0200 From: Heiko Stuebner To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 4/6] ARM: dts: rockchip: add Cortex-A9 SPI controller nodes Date: Wed, 10 Sep 2014 20:46:53 +0200 Message-Id: <1410374815-20208-5-git-send-email-heiko@sntech.de> X-Mailer: git-send-email 2.0.1 In-Reply-To: <1410374815-20208-1-git-send-email-heiko@sntech.de> References: <1410374815-20208-1-git-send-email-heiko@sntech.de> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140910_114507_241658_1FAF48AF X-CRM114-Status: UNSURE ( 5.89 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -2.5 (--) Cc: linux-rockchip@lists.infradead.org, Heiko Stuebner X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This adds basic spi nodes and pinctrl settings to the rk3066 and rk3188 devicetree files. Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3066a.dtsi | 46 ++++++++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/rk3188.dtsi | 48 ++++++++++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/rk3xxx.dtsi | 24 +++++++++++++++++++++ 3 files changed, 118 insertions(+) diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index 879a818..8021eed 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -238,6 +238,42 @@ }; }; + spi0 { + spi0_clk: spi0-clk { + rockchip,pins = ; + }; + spi0_cs0: spi0-cs0 { + rockchip,pins = ; + }; + spi0_tx: spi0-tx { + rockchip,pins = ; + }; + spi0_rx: spi0-rx { + rockchip,pins = ; + }; + spi0_cs1: spi0-cs1 { + rockchip,pins = ; + }; + }; + + spi1 { + spi1_clk: spi1-clk { + rockchip,pins = ; + }; + spi1_cs0: spi1-cs0 { + rockchip,pins = ; + }; + spi1_rx: spi1-rx { + rockchip,pins = ; + }; + spi1_tx: spi1-tx { + rockchip,pins = ; + }; + spi1_cs1: spi1-cs1 { + rockchip,pins = ; + }; + }; + uart0 { uart0_xfer: uart0-xfer { rockchip,pins = , @@ -406,6 +442,16 @@ pinctrl-0 = <&pwm3_out>; }; +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_xfer>; diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index ee801a9..573ef61 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -206,6 +206,42 @@ }; }; + spi0 { + spi0_clk: spi0-clk { + rockchip,pins = ; + }; + spi0_cs0: spi0-cs0 { + rockchip,pins = ; + }; + spi0_tx: spi0-tx { + rockchip,pins = ; + }; + spi0_rx: spi0-rx { + rockchip,pins = ; + }; + spi0_cs1: spi0-cs1 { + rockchip,pins = ; + }; + }; + + spi1 { + spi1_clk: spi1-clk { + rockchip,pins = ; + }; + spi1_cs0: spi1-cs0 { + rockchip,pins = ; + }; + spi1_rx: spi1-rx { + rockchip,pins = ; + }; + spi1_tx: spi1-tx { + rockchip,pins = ; + }; + spi1_cs1: spi1-cs1 { + rockchip,pins = ; + }; + }; + uart0 { uart0_xfer: uart0-xfer { rockchip,pins = , @@ -381,6 +417,18 @@ pinctrl-0 = <&pwm3_out>; }; +&spi0 { + compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; +}; + +&spi1 { + compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_xfer>; diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi index c873624..7bcd698 100644 --- a/arch/arm/boot/dts/rk3xxx.dtsi +++ b/arch/arm/boot/dts/rk3xxx.dtsi @@ -26,6 +26,8 @@ i2c2 = &i2c2; i2c3 = &i2c3; i2c4 = &i2c4; + spi0 = &spi0; + spi1 = &spi1; }; xin24m: oscillator { @@ -291,4 +293,26 @@ clock-names = "saradc", "apb_pclk"; status = "disabled"; }; + + spi0: spi@20070000 { + compatible = "rockchip,rk3066-spi"; + clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; + clock-names = "spiclk", "apb_pclk"; + interrupts = ; + reg = <0x20070000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@20074000 { + compatible = "rockchip,rk3066-spi"; + clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; + clock-names = "spiclk", "apb_pclk"; + interrupts = ; + reg = <0x20074000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; };