| Message ID | 1411572802-22042-4-git-send-email-kever.yang@rock-chips.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Kever, On Wed, Sep 24, 2014 at 8:33 AM, Kever Yang <kever.yang@rock-chips.com> wrote: > This patch add the clock node in PD_VIDEO > > Signed-off-by: Kever Yang <kever.yang@rock-chips.com> > Reviewed-by: Heiko Stuebner <heiko@sntech.de> > --- > > Changes in v2: > - split out the patch > > drivers/clk/rockchip/clk-rk3288.c | 11 +++++++++++ > 1 file changed, 11 insertions(+) > > diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c > index d691a56..2cfcfb6 100644 > --- a/drivers/clk/rockchip/clk-rk3288.c > +++ b/drivers/clk/rockchip/clk-rk3288.c > @@ -296,6 +296,17 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { > COMPOSITE(0, "aclk_vdpu", mux_pll_src_cpll_gpll_usb480m_p, 0, > RK3288_CLKSEL_CON(32), 14, 2, MFLAGS, 8, 5, DFLAGS, > RK3288_CLKGATE_CON(3), 11, GFLAGS), > + /* > + * We use aclk_vdpu by default GRF_SOC_CON0[7] setting in system, > + * so we ignore the mux and make clocks nodes as following, I guess we can't add the mux for now because it's in the GRF and not in the clock area and the current clock tables don't have support for that. I guess that OK for now, but eventually we should probably add it in. > + * NOTE THAT hclk_vcodec is fix div by 4 from aclk_vcodec_pre. Typo: from "aclk_vcodec_pre" or from "hclk_vcodec_pre"? > + */ > + GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vdpu", 0, > + RK3288_CLKGATE_CON(9), 0, GFLAGS), > + GATE(0, "hclk_vcodec_pre", "aclk_vdpu", 0, > + RK3288_CLKGATE_CON(3), 10, GFLAGS), > + GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", 0, > + RK3288_CLKGATE_CON(9), 1, GFLAGS), Shouldn't there be a fixed "/ 4" clock somewhere in here? That way the clock rate will be reported correctly? I guess the cleanest would be to add support to rockchip/clk.c to call clk_register_fixed_factor() somehow. I guess I'll leave it to you and Heiko to decide what you want to do here. -Doug
Hi Doug, On 09/25/2014 03:48 AM, Doug Anderson wrote: > Kever, > > On Wed, Sep 24, 2014 at 8:33 AM, Kever Yang <kever.yang@rock-chips.com> wrote: >> This patch add the clock node in PD_VIDEO >> >> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> >> Reviewed-by: Heiko Stuebner <heiko@sntech.de> >> --- >> >> Changes in v2: >> - split out the patch >> >> drivers/clk/rockchip/clk-rk3288.c | 11 +++++++++++ >> 1 file changed, 11 insertions(+) >> >> diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c >> index d691a56..2cfcfb6 100644 >> --- a/drivers/clk/rockchip/clk-rk3288.c >> +++ b/drivers/clk/rockchip/clk-rk3288.c >> @@ -296,6 +296,17 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { >> COMPOSITE(0, "aclk_vdpu", mux_pll_src_cpll_gpll_usb480m_p, 0, >> RK3288_CLKSEL_CON(32), 14, 2, MFLAGS, 8, 5, DFLAGS, >> RK3288_CLKGATE_CON(3), 11, GFLAGS), >> + /* >> + * We use aclk_vdpu by default GRF_SOC_CON0[7] setting in system, >> + * so we ignore the mux and make clocks nodes as following, > I guess we can't add the mux for now because it's in the GRF and not > in the clock area and the current clock tables don't have support for > that. I guess that OK for now, but eventually we should probably add > it in. The mux setting moved to GRF because it switch the clock source and some other controller logic. The VCODEC can be used as encoder or decoder, we use it as decoder by default, so I guess we can ignore the decoder part before the clock module can handle this. > > >> + * NOTE THAT hclk_vcodec is fix div by 4 from aclk_vcodec_pre. > Typo: from "aclk_vcodec_pre" or from "hclk_vcodec_pre"? hclk_vcodec_pre is /4 from aclk_vcodec_pre, and hclk_vcodec has a gate from hclk_vcodec_pre. I should fix this. > >> + */ >> + GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vdpu", 0, >> + RK3288_CLKGATE_CON(9), 0, GFLAGS), >> + GATE(0, "hclk_vcodec_pre", "aclk_vdpu", 0, >> + RK3288_CLKGATE_CON(3), 10, GFLAGS), >> + GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", 0, >> + RK3288_CLKGATE_CON(9), 1, GFLAGS), > Shouldn't there be a fixed "/ 4" clock somewhere in here? That way > the clock rate will be reported correctly? > > I guess the cleanest would be to add support to rockchip/clk.c to call > clk_register_fixed_factor() somehow. I guess I'll leave it to you and > Heiko to decide what you want to do here. There is a fixed "/4" that not add to this tree, which makes we get a 4 times of real rate when we get the HCLK_VCODEC, that is why I write a commend with "NOTE THAT" before. I know there is a clk_register_fixed_factor(), but I'm not sure how to use it here, this is a table. I'll try to add the clk_register_fixed_factor() today. -Kever
diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c index d691a56..2cfcfb6 100644 --- a/drivers/clk/rockchip/clk-rk3288.c +++ b/drivers/clk/rockchip/clk-rk3288.c @@ -296,6 +296,17 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { COMPOSITE(0, "aclk_vdpu", mux_pll_src_cpll_gpll_usb480m_p, 0, RK3288_CLKSEL_CON(32), 14, 2, MFLAGS, 8, 5, DFLAGS, RK3288_CLKGATE_CON(3), 11, GFLAGS), + /* + * We use aclk_vdpu by default GRF_SOC_CON0[7] setting in system, + * so we ignore the mux and make clocks nodes as following, + * NOTE THAT hclk_vcodec is fix div by 4 from aclk_vcodec_pre. + */ + GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vdpu", 0, + RK3288_CLKGATE_CON(9), 0, GFLAGS), + GATE(0, "hclk_vcodec_pre", "aclk_vdpu", 0, + RK3288_CLKGATE_CON(3), 10, GFLAGS), + GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", 0, + RK3288_CLKGATE_CON(9), 1, GFLAGS), COMPOSITE(0, "aclk_vio0", mux_pll_src_cpll_gpll_usb480m_p, 0, RK3288_CLKSEL_CON(31), 6, 2, MFLAGS, 0, 5, DFLAGS,