From patchwork Tue Oct 21 17:47:35 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 5127331 Return-Path: X-Original-To: patchwork-linux-rockchip@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 646FA9F387 for ; Tue, 21 Oct 2014 17:54:46 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 80BD52021F for ; Tue, 21 Oct 2014 17:54:45 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8F9EF20225 for ; Tue, 21 Oct 2014 17:54:44 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Xgddq-0003u7-8Z; Tue, 21 Oct 2014 17:54:42 +0000 Received: from mail-pa0-x233.google.com ([2607:f8b0:400e:c03::233]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1XgdXW-0004VJ-Em for linux-rockchip@lists.infradead.org; Tue, 21 Oct 2014 17:48:11 +0000 Received: by mail-pa0-f51.google.com with SMTP id lj1so1872015pab.38 for ; Tue, 21 Oct 2014 10:47:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=49DDud9vTmzz852r8b0iP9ItSKuu28MwbSLMxESZITE=; b=Zjy7d9eeVd9+ydNfTKHsaFT4JZWme0waPQij0CpJnbLmkatWCWz1dVKSkLKB3IzdjM eXYVP8nQXdZVd+0vP1DaORfkayFpU3kVsicmc9+C1eLgoJOxV0WFDgv2jMArCccoZIFg TtjjoIE3zVPXLGlorDe7cBinQ+QtCiu8Q0dPs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=49DDud9vTmzz852r8b0iP9ItSKuu28MwbSLMxESZITE=; b=KwVivrw7ADhSE90y+J0DCwEHY8nyoT74saIfnv2DzNU9z0jKhy/DuHME04QglZHp3V 8M2L4/+uo2cA6Cjum4IfZkfdYCf4B5dsF1gk8B/zJa3xfd4cYGQwHnk8a2tHMj9PYs8j qusSd3QL0SLANRGKolafqe/rGnqqGRwtKA+t2KD20hPjhnadIPN6swR7VZeiBzR7aKGU zl3zk7UVNcRwwNm1QTBAkY565cKeJtnq3SinqnaUwUTlZGWpkw02ck6Gc1KXcarNvCRJ iSIGJ6z2iht+Eu4z6Wggq+nAjD2QeS4QWHRBetRDGeDnL+IJatcnhqhkCtehI5SBIKzM AdfQ== X-Gm-Message-State: ALoCoQm0BHM24RIHCUHBd7doe4xF5oQTgcG8MskARNV9OpTzP3A0CO+fNXMD38hL1wFfxs6n7MbZ X-Received: by 10.67.13.205 with SMTP id fa13mr12737948pad.118.1413913666965; Tue, 21 Oct 2014 10:47:46 -0700 (PDT) Received: from tictac.mtv.corp.google.com ([172.22.162.15]) by mx.google.com with ESMTPSA id ky4sm12336911pbc.55.2014.10.21.10.47.46 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 21 Oct 2014 10:47:46 -0700 (PDT) From: Doug Anderson To: Linus Walleij , Heiko Stuebner Subject: [PATCH v2 4/4] pinctrl: rockchip: Protect read-modify-write with the spinlock Date: Tue, 21 Oct 2014 10:47:35 -0700 Message-Id: <1413913655-22351-4-git-send-email-dianders@chromium.org> X-Mailer: git-send-email 2.1.0.rc2.206.gedb03e5 In-Reply-To: <1413913655-22351-1-git-send-email-dianders@chromium.org> References: <1413913655-22351-1-git-send-email-dianders@chromium.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20141021_104810_550066_66794AE8 X-CRM114-Status: GOOD ( 11.54 ) X-Spam-Score: -0.8 (/) Cc: Doug Anderson , linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, Chris Zhong , Sonny Rao , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-3.2 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_NONE,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP There were a few instances where the rockchip pinctrl driver would do read-modify-write with no spinlock. Add a spinlock for these cases. Signed-off-by: Doug Anderson Reviewed-by: Heiko Stuebner --- Changes in v2: - Made sure to release the lock in an error condition. drivers/pinctrl/pinctrl-rockchip.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 6c14f6c..59a5461 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -861,6 +861,7 @@ static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip, { struct rockchip_pin_bank *bank; int ret; + unsigned long flags; u32 data; bank = gc_to_pin_bank(chip); @@ -869,6 +870,8 @@ static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip, if (ret < 0) return ret; + spin_lock_irqsave(&bank->slock, flags); + data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); /* set bit to 1 for output, 0 for input */ if (!input) @@ -877,6 +880,8 @@ static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip, data &= ~BIT(pin); writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); + spin_unlock_irqrestore(&bank->slock, flags); + return 0; } @@ -1394,6 +1399,7 @@ static void rockchip_irq_demux(unsigned int irq, struct irq_desc *desc) u32 polarity = 0, data = 0; u32 pend; bool edge_changed = false; + unsigned long flags; dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name); @@ -1439,10 +1445,14 @@ static void rockchip_irq_demux(unsigned int irq, struct irq_desc *desc) if (bank->toggle_edge_mode && edge_changed) { /* Interrupt params should only be set with ints disabled */ + spin_lock_irqsave(&bank->slock, flags); + data = readl_relaxed(bank->reg_base + GPIO_INTEN); writel_relaxed(0, bank->reg_base + GPIO_INTEN); writel(polarity, bank->reg_base + GPIO_INT_POLARITY); writel(data, bank->reg_base + GPIO_INTEN); + + spin_unlock_irqrestore(&bank->slock, flags); } chained_irq_exit(chip, desc); @@ -1456,6 +1466,7 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type) u32 polarity; u32 level; u32 data; + unsigned long flags; int ret; /* make sure the pin is configured as gpio input */ @@ -1463,15 +1474,20 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type) if (ret < 0) return ret; + spin_lock_irqsave(&bank->slock, flags); + data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); data &= ~mask; writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); + spin_unlock_irqrestore(&bank->slock, flags); + if (type & IRQ_TYPE_EDGE_BOTH) __irq_set_handler_locked(d->irq, handle_edge_irq); else __irq_set_handler_locked(d->irq, handle_level_irq); + spin_lock_irqsave(&bank->slock, flags); irq_gc_lock(gc); level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL); @@ -1514,6 +1530,7 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type) break; default: irq_gc_unlock(gc); + spin_unlock_irqrestore(&bank->slock, flags); return -EINVAL; } @@ -1521,6 +1538,7 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type) writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY); irq_gc_unlock(gc); + spin_unlock_irqrestore(&bank->slock, flags); return 0; }