From patchwork Mon Nov 3 19:05:31 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Soren Brinkmann X-Patchwork-Id: 5219281 Return-Path: X-Original-To: patchwork-linux-rockchip@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id C088B9F349 for ; Mon, 3 Nov 2014 19:07:56 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 9D5A62012F for ; Mon, 3 Nov 2014 19:07:55 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9100920127 for ; Mon, 3 Nov 2014 19:07:54 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XlMyn-0007Nz-Th; Mon, 03 Nov 2014 19:07:53 +0000 Received: from mail-qg0-x22d.google.com ([2607:f8b0:400d:c04::22d]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1XlMxa-0006Gq-0k; Mon, 03 Nov 2014 19:06:39 +0000 Received: by mail-qg0-f45.google.com with SMTP id z107so9262129qgd.32 for ; Mon, 03 Nov 2014 11:06:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=/7EzmLReLG5XbHaWEVZZvuWdL6xaz8eYc5qDMqgvGVc=; b=AhKGwAyatU3+j8YIoVqacpss0qXusNztHj3d5kDnVQkmkXZBQ+8st9nsiCTghrza6v rwY+vFORgyqbDazufJWwSu2dnpxT1vKn60LtbwJLrfzPhlOs6ScnyM4lHS3QbS3y2BiA eudKMXSOMkhXCw1lFJVok5tOeedAm1PeagIJzdMjGUBK9JfseL2v7VtkI3jMdDLdfupA atDWfYWdqoGq/ohW23A0el8L9QdrNiMdiZc790IpY3eug5iTFT04p8kzya3+iIHWnA8Y ccGwFicrSysy6VGUL+n/ooabHB6B93uHzKs43dzlb9zG0XL2vpODr4B/th1rQRC63kX5 PWnA== X-Received: by 10.224.8.66 with SMTP id g2mr57028515qag.12.1415041575928; Mon, 03 Nov 2014 11:06:15 -0800 (PST) Received: from localhost ([149.199.62.254]) by mx.google.com with ESMTPSA id j17sm17585023qae.10.2014.11.03.11.06.14 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Mon, 03 Nov 2014 11:06:15 -0800 (PST) From: Soren Brinkmann To: Linus Walleij Subject: [PATCH 7/7] ARM: zynq: DT: Add pinctrl information Date: Mon, 3 Nov 2014 11:05:31 -0800 Message-Id: <1415041531-15520-8-git-send-email-soren.brinkmann@xilinx.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1415041531-15520-1-git-send-email-soren.brinkmann@xilinx.com> References: <1415041531-15520-1-git-send-email-soren.brinkmann@xilinx.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20141103_110638_213143_2AC4395D X-CRM114-Status: UNSURE ( 8.73 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -0.7 (/) Cc: Laurent Pinchart , Heiko Stuebner , linux-sh@vger.kernel.org, Michal Simek , linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, =?UTF-8?q?S=C3=B6ren=20Brinkmann?= , linux-arm-kernel@lists.infradead.org, Alessandro Rubini X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_NONE,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add pinctrl descriptions to the zc702 and zc706 device trees. Signed-off-by: Soren Brinkmann --- Changes since RFC v2: - add pinconf properties to zc702 mdio node - remove arguments from bias-related props Changes since RFC v1: - separate DT changes into their own patch --- arch/arm/boot/dts/zynq-7000.dtsi | 8 ++- arch/arm/boot/dts/zynq-zc702.dts | 143 +++++++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/zynq-zc706.dts | 120 ++++++++++++++++++++++++++++++++ 3 files changed, 270 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi index ce2ef5bec4f2..fc5246a4f69f 100644 --- a/arch/arm/boot/dts/zynq-7000.dtsi +++ b/arch/arm/boot/dts/zynq-7000.dtsi @@ -237,7 +237,7 @@ slcr: slcr@f8000000 { #address-cells = <1>; #size-cells = <1>; - compatible = "xlnx,zynq-slcr", "syscon"; + compatible = "xlnx,zynq-slcr", "syscon", "simple-bus"; reg = <0xF8000000 0x1000>; ranges; clkc: clkc@100 { @@ -258,6 +258,12 @@ "dbg_trc", "dbg_apb"; reg = <0x100 0x100>; }; + + pinctrl0: pinctrl@700 { + compatible = "xlnx,pinctrl-zynq"; + reg = <0x700 0x200>; + syscon = <&slcr>; + }; }; dmac_s: dmac@f8003000 { diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts index 94e2cda6f9b6..f64e7ad53c65 100644 --- a/arch/arm/boot/dts/zynq-zc702.dts +++ b/arch/arm/boot/dts/zynq-zc702.dts @@ -40,21 +40,32 @@ &can0 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can0_default>; }; &gem0 { status = "okay"; phy-mode = "rgmii-id"; phy-handle = <ðernet_phy>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gem0_default>; ethernet_phy: ethernet-phy@7 { reg = <7>; }; }; +&gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio0_default>; +}; + &i2c0 { status = "okay"; clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_default>; i2cswitch@74 { compatible = "nxp,pca9548"; @@ -128,10 +139,142 @@ }; }; +&pinctrl0 { + pinctrl_can0_default: pinctrl-can0-default { + common { + function = "can0"; + groups = "can0_9_grp"; + slew-rate = <0>; + io-standard = <1>; + }; + + rx { + pins = "MIO46"; + bias-high-impedance; + }; + + tx { + pins = "MIO47"; + bias-disable; + }; + }; + + pinctrl_gem0_default: pinctrl-gem0-default { + common { + function = "ethernet0"; + groups = "ethernet0_0_grp"; + slew-rate = <0>; + io-standard = <4>; + }; + + rx { + pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27"; + bias-high-impedance; + low-power-disable; + }; + + tx { + pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21"; + bias-disable; + low-power-enable; + }; + + mdio { + function = "mdio0"; + groups = "mdio0_0_grp"; + slew-rate = <0>; + io-standard = <1>; + bias-disable; + }; + }; + + pinctrl_gpio0_default: pinctrl-gpio0-default { + common { + function = "gpio0"; + groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp", + "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp", + "gpio0_13_grp", "gpio0_14_grp"; + slew-rate = <0>; + io-standard = <1>; + }; + + pull-up { + pins = "MIO9", "MIO10", "MIO11", "MIO12", "MIO13", "MIO14"; + bias-pull-up; + }; + + pull-none { + pins = "MIO7", "MIO8"; + bias-disable; + }; + }; + + pinctrl_i2c0_default: pinctrl-i2c0-default { + common { + groups = "i2c0_10_grp"; + function = "i2c0"; + bias-pull-up; + slew-rate = <0>; + io-standard = <1>; + }; + }; + + pinctrl_sdhci0_default: pinctrl-sdhci0-default { + common { + groups = "sdio0_2_grp"; + function = "sdio0"; + slew-rate = <0>; + io-standard = <1>; + bias-disable; + }; + + cd { + groups = "gpio0_0_grp"; + function = "sdio0_cd"; + bias-high-impedance; + bias-pull-up; + slew-rate = <0>; + io-standard = <1>; + }; + + wp { + groups = "gpio0_15_grp"; + function = "sdio0_wp"; + bias-high-impedance; + bias-pull-up; + slew-rate = <0>; + io-standard = <1>; + }; + }; + + pinctrl_uart1_default: pinctrl-uart1-default { + common { + groups = "uart1_10_grp"; + function = "uart1"; + slew-rate = <0>; + io-standard = <1>; + }; + + rx { + pins = "MIO49"; + bias-high-impedance; + }; + + tx { + pins = "MIO48"; + bias-disable = <0>; + }; + }; +}; + &sdhci0 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhci0_default>; }; &uart1 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_default>; }; diff --git a/arch/arm/boot/dts/zynq-zc706.dts b/arch/arm/boot/dts/zynq-zc706.dts index a8bbdfbc7093..5575a175f867 100644 --- a/arch/arm/boot/dts/zynq-zc706.dts +++ b/arch/arm/boot/dts/zynq-zc706.dts @@ -33,15 +33,24 @@ status = "okay"; phy-mode = "rgmii-id"; phy-handle = <ðernet_phy>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gem0_default>; ethernet_phy: ethernet-phy@7 { reg = <7>; }; }; +&gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio0_default>; +}; + &i2c0 { status = "okay"; clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_default>; i2cswitch@74 { compatible = "nxp,pca9548"; @@ -107,10 +116,121 @@ }; }; +&pinctrl0 { + pinctrl_gem0_default: pinctrl-gem0-default { + common { + function = "ethernet0"; + groups = "ethernet0_0_grp"; + slew-rate = <0>; + io-standard = <4>; + }; + + rx { + pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27"; + bias-high-impedance; + low-power-disable; + }; + + tx { + pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21"; + low-power-enable; + bias-disable; + }; + + mdio { + function = "mdio0"; + groups = "mdio0_0_grp"; + slew-rate = <0>; + io-standard = <1>; + bias-disable; + }; + }; + + pinctrl_gpio0_default: pinctrl-gpio0-default { + common { + function = "gpio0"; + groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp"; + slew-rate = <0>; + io-standard = <1>; + }; + + pull-up { + pins = "MIO46", "MIO47"; + bias-pull-up; + }; + + pull-none { + pins = "MIO7"; + bias-disable; + }; + }; + + pinctrl_i2c0_default: pinctrl-i2c0-default { + common { + groups = "i2c0_10_grp"; + function = "i2c0"; + bias-pull-up; + slew-rate = <0>; + io-standard = <1>; + }; + }; + + pinctrl_sdhci0_default: pinctrl-sdhci0-default { + common { + groups = "sdio0_2_grp"; + function = "sdio0"; + slew-rate = <0>; + io-standard = <1>; + bias-disable; + }; + + cd { + groups = "gpio0_14_grp"; + function = "sdio0_cd"; + bias-high-impedance; + bias-pull-up; + slew-rate = <0>; + io-standard = <1>; + }; + + wp { + groups = "gpio0_15_grp"; + function = "sdio0_wp"; + bias-high-impedance; + bias-pull-up; + slew-rate = <0>; + io-standard = <1>; + }; + }; + + pinctrl_uart1_default: pinctrl-uart1-default { + common { + groups = "uart1_10_grp"; + function = "uart1"; + slew-rate = <0>; + io-standard = <1>; + }; + + rx { + pins = "MIO49"; + bias-high-impedance; + }; + + tx { + pins = "MIO48"; + bias-disable; + }; + }; +}; + &sdhci0 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhci0_default>; }; &uart1 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_default>; };