| Message ID | 1417661375-2872-1-git-send-email-addy.ke@rock-chips.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Addy, On Wed, Dec 3, 2014 at 6:49 PM, Addy Ke <addy.ke@rock-chips.com> wrote: > All of mmc controllers include SDMMC, SDIO0, SDIO1, and EMMC on RK3288 > are limited to 150Mhz. It was mainly caused by two reasons: > - RK3288's IO pad(except DDR IO pad) is generic, which can only support > the max of 150Mhz. > - Mmc controller was designed at 150Mhz, and the pressure test by IC team > was based on this freequency point. > > Signed-off-by: Addy Ke <addy.ke@rock-chips.com> > --- > arch/arm/boot/dts/rk3288.dtsi | 4 ++++ > 1 file changed, 4 insertions(+) Your explanation is reasonable. The 150MHz rate is also listed in the latest datasheet. It's unfortunate that we won't get full speed of SDR104 or hs200 on this SoC, but correctness certainly outweighs performance. Reviewed-by: Doug Anderson <dianders@chromium.org> I have tested that this prevents the speed from going above 150MHz on rk3288-pinky on SD Cards, so: Tested-by: Doug Anderson <dianders@chromium.org> -Doug
Am Donnerstag, 4. Dezember 2014, 10:49:35 schrieb Addy Ke: > All of mmc controllers include SDMMC, SDIO0, SDIO1, and EMMC on RK3288 > are limited to 150Mhz. It was mainly caused by two reasons: > - RK3288's IO pad(except DDR IO pad) is generic, which can only support > the max of 150Mhz. > - Mmc controller was designed at 150Mhz, and the pressure test by IC team > was based on this freequency point. > > Signed-off-by: Addy Ke <addy.ke@rock-chips.com> applied to my wip dts branch for 3.20 (on github) Thanks Heiko
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index acb6a2f..9c35a1d 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -149,6 +149,7 @@ sdmmc: dwmmc@ff0c0000 { compatible = "rockchip,rk3288-dw-mshc"; + clock-freq-min-max = <400000 150000000>; clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; clock-names = "biu", "ciu"; fifo-depth = <0x100>; @@ -159,6 +160,7 @@ sdio0: dwmmc@ff0d0000 { compatible = "rockchip,rk3288-dw-mshc"; + clock-freq-min-max = <400000 150000000>; clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>; clock-names = "biu", "ciu"; fifo-depth = <0x100>; @@ -169,6 +171,7 @@ sdio1: dwmmc@ff0e0000 { compatible = "rockchip,rk3288-dw-mshc"; + clock-freq-min-max = <400000 150000000>; clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>; clock-names = "biu", "ciu"; fifo-depth = <0x100>; @@ -179,6 +182,7 @@ emmc: dwmmc@ff0f0000 { compatible = "rockchip,rk3288-dw-mshc"; + clock-freq-min-max = <400000 150000000>; clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>; clock-names = "biu", "ciu"; fifo-depth = <0x100>;
All of mmc controllers include SDMMC, SDIO0, SDIO1, and EMMC on RK3288 are limited to 150Mhz. It was mainly caused by two reasons: - RK3288's IO pad(except DDR IO pad) is generic, which can only support the max of 150Mhz. - Mmc controller was designed at 150Mhz, and the pressure test by IC team was based on this freequency point. Signed-off-by: Addy Ke <addy.ke@rock-chips.com> --- arch/arm/boot/dts/rk3288.dtsi | 4 ++++ 1 file changed, 4 insertions(+)