From patchwork Thu Dec 11 09:55:18 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LiYunzhi X-Patchwork-Id: 5474871 Return-Path: X-Original-To: patchwork-linux-rockchip@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id E2EA4BEEA8 for ; Thu, 11 Dec 2014 09:58:14 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C939B201BB for ; Thu, 11 Dec 2014 09:58:13 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5C1162018E for ; Thu, 11 Dec 2014 09:58:12 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Xz0Vf-0001zI-1q; Thu, 11 Dec 2014 09:58:11 +0000 Received: from lucky1.263xmail.com ([211.157.147.130]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Xz0VH-0001db-Rg; Thu, 11 Dec 2014 09:57:50 +0000 Received: from lyz?rock-chips.com (unknown [192.168.167.12]) by lucky1.263xmail.com (Postfix) with SMTP id 3ECF319A0D7; Thu, 11 Dec 2014 17:57:19 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 1 X-MAIL-DELIVERY: 0 X-KSVirus-check: 0 X-ABS-CHECKED: 4 Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.263.net (Postfix) with ESMTP id 5BF5E3F4; Thu, 11 Dec 2014 17:57:17 +0800 (CST) X-RL-SENDER: lyz@rock-chips.com X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: lyz@rock-chips.com X-UNIQUE-TAG: <5edd0680ea2c8812c60f8c8dfd301cc5> X-ATTACHMENT-NUM: 0 X-SENDER: lyz@rock-chips.com X-DNS-TYPE: 0 Received: from unknown (unknown [58.22.7.114]) by smtp.263.net (Postfix) whith SMTP id 84765MEEQC; Thu, 11 Dec 2014 17:57:18 +0800 (CST) From: Yunzhi Li To: heiko@sntech.de, jwerner@chromium.org, dianders@chromium.org Subject: [PATCH v6 1/5] phy: add a driver for the Rockchip SoC internal USB2.0 PHY Date: Thu, 11 Dec 2014 17:55:18 +0800 Message-Id: <1418291722-25448-2-git-send-email-lyz@rock-chips.com> X-Mailer: git-send-email 2.0.0 In-Reply-To: <1418291722-25448-1-git-send-email-lyz@rock-chips.com> References: <1418291722-25448-1-git-send-email-lyz@rock-chips.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20141211_015748_455532_727AD5F6 X-CRM114-Status: GOOD ( 17.46 ) X-Spam-Score: -0.0 (/) Cc: huangtao@rock-chips.com, devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Kishon Vijay Abraham I , zyw@rock-chips.com, Rob Herring , Yunzhi Li , olof@lixom.net, cf@rock-chips.com, linux-arm-kernel@lists.infradead.org, Grant Likely X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch to add a generic PHY driver for ROCKCHIP usb PHYs, currently this driver can support RK3288. The RK3288 SoC have three independent USB PHY IPs which are all configured through a set of registers located in the GRF (general register files) module. Signed-off-by: Yunzhi Li --- Changes in v6: - Rename SIDDQ_MSK to SIDDQ_WRITE_ENA. - Use phandle args to find a phy struct directly. Changes in v5: None Changes in v4: - Get number of PHYs from device tree. - Model each PHY as subnode of the phy provider node. Changes in v3: - Use BIT macro instead of bit shift ops. - Rename the config entry to PHY_ROCKCHIP_USB. drivers/phy/Kconfig | 7 ++ drivers/phy/Makefile | 1 + drivers/phy/phy-rockchip-usb.c | 198 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 206 insertions(+) create mode 100644 drivers/phy/phy-rockchip-usb.c diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index ccad880..b24500a 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -239,6 +239,13 @@ config PHY_QCOM_IPQ806X_SATA depends on OF select GENERIC_PHY +config PHY_ROCKCHIP_USB + tristate "Rockchip USB2 PHY Driver" + depends on ARCH_ROCKCHIP && OF + select GENERIC_PHY + help + Enable this to support the Rockchip USB 2.0 PHY. + config PHY_ST_SPEAR1310_MIPHY tristate "ST SPEAR1310-MIPHY driver" select GENERIC_PHY diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index aa74f96..48bf5a1 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -28,6 +28,7 @@ phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2) += phy-exynos5250-usb2.o phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2) += phy-s5pv210-usb2.o obj-$(CONFIG_PHY_EXYNOS5_USBDRD) += phy-exynos5-usbdrd.o obj-$(CONFIG_PHY_QCOM_APQ8064_SATA) += phy-qcom-apq8064-sata.o +obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY) += phy-spear1310-miphy.o obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY) += phy-spear1340-miphy.o diff --git a/drivers/phy/phy-rockchip-usb.c b/drivers/phy/phy-rockchip-usb.c new file mode 100644 index 0000000..dad5194 --- /dev/null +++ b/drivers/phy/phy-rockchip-usb.c @@ -0,0 +1,198 @@ +/* + * Rockchip usb PHY driver + * + * Copyright (C) 2014 Yunzhi Li + * Copyright (C) 2014 ROCKCHIP, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define ROCKCHIP_RK3288_UOC(n) (0x320 + n * 0x14) + +/* + * The higher 16-bit of this register is used for write protection + * only if BIT(13 + 16) set to 1 the BIT(13) can be written. + */ +#define SIDDQ_WRITE_ENA BIT(29) +#define SIDDQ_ON BIT(13) +#define SIDDQ_OFF (0 << 13) + +struct rockchip_usb_phy { + struct regmap *reg_base; + unsigned int reg_offset; + struct clk *clk; + struct phy *phy; +}; + +struct rockchip_usb_phy_priv { + struct rockchip_usb_phy *phys; + unsigned nphys; +}; + +static int rockchip_usb_phy_power(struct rockchip_usb_phy *phy, + bool siddq) +{ + return regmap_write(phy->reg_base, phy->reg_offset, + SIDDQ_WRITE_ENA | (siddq ? SIDDQ_ON : SIDDQ_OFF)); +} + +static int rockchip_usb_phy_power_off(struct phy *_phy) +{ + struct rockchip_usb_phy *phy = phy_get_drvdata(_phy); + int ret = 0; + + /* Power down usb phy analog blocks by set siddq 1 */ + ret = rockchip_usb_phy_power(phy, 1); + if (ret) + return ret; + + clk_disable_unprepare(phy->clk); + if (ret) + return ret; + + return 0; +} + +static int rockchip_usb_phy_power_on(struct phy *_phy) +{ + struct rockchip_usb_phy *phy = phy_get_drvdata(_phy); + int ret = 0; + + ret = clk_prepare_enable(phy->clk); + if (ret) + return ret; + + /* Power up usb phy analog blocks by set siddq 0 */ + ret = rockchip_usb_phy_power(phy, 0); + if (ret) + return ret; + + return 0; +} + +static struct phy *rockchip_usb_phy_xlate(struct device *dev, + struct of_phandle_args *args) +{ + struct rockchip_usb_phy_priv *priv = dev_get_drvdata(dev); + unsigned int phy_id = args->args[0]; + + if (WARN_ON(phy_id < 0 || phy_id >= priv->nphys)) + return ERR_PTR(-ENODEV); + + return priv->phys[phy_id].phy; +} + +static struct phy_ops ops = { + .power_on = rockchip_usb_phy_power_on, + .power_off = rockchip_usb_phy_power_off, + .owner = THIS_MODULE, +}; + +static int rockchip_usb_phy_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct rockchip_usb_phy *rk_phy; + struct rockchip_usb_phy_priv *priv; + struct phy_provider *phy_provider; + struct device_node *child; + struct regmap *grf; + unsigned int phy_id; + + grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,grf"); + if (IS_ERR(grf)) { + dev_err(&pdev->dev, "Missing rockchip,grf property\n"); + return PTR_ERR(grf); + } + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + /* Get number of phys from device tree */ + priv->nphys = of_get_child_count(dev->of_node); + if (priv->nphys == 0) + return -ENODEV; + + priv->phys = devm_kzalloc(dev, priv->nphys * sizeof(*priv->phys), + GFP_KERNEL); + if (!priv->phys) + return -ENOMEM; + + for_each_available_child_of_node(dev->of_node, child) { + if (of_property_read_u32(child, "reg", &phy_id)) { + dev_err(dev, "missing reg property in node %s\n", + child->name); + return -EINVAL; + } + + if (phy_id < 0 || phy_id >= priv->nphys) { + dev_err(dev, "invalid phy id\n"); + return -EINVAL; + } + rk_phy = &priv->phys[phy_id]; + rk_phy->reg_offset = ROCKCHIP_RK3288_UOC(phy_id); + rk_phy->reg_base = grf; + + rk_phy->clk = of_clk_get(child, 0); + if (IS_ERR(rk_phy->clk)) { + dev_warn(dev, "failed to get clock\n"); + rk_phy->clk = NULL; + } + + rk_phy->phy = devm_phy_create(dev, NULL, &ops); + if (IS_ERR(rk_phy->phy)) { + dev_err(dev, "failed to create PHY %d\n", phy_id); + return PTR_ERR(rk_phy->phy); + } + phy_set_drvdata(rk_phy->phy, rk_phy); + } + + platform_set_drvdata(pdev, priv); + + phy_provider = devm_of_phy_provider_register(dev, + rockchip_usb_phy_xlate); + return PTR_ERR_OR_ZERO(phy_provider); +} + +static const struct of_device_id rockchip_usb_phy_dt_ids[] = { + { .compatible = "rockchip,rk3288-usb-phy" }, + {} +}; + +MODULE_DEVICE_TABLE(of, rockchip_usb_phy_dt_ids); + +static struct platform_driver rockchip_usb_driver = { + .probe = rockchip_usb_phy_probe, + .driver = { + .name = "rockchip-usb-phy", + .owner = THIS_MODULE, + .of_match_table = rockchip_usb_phy_dt_ids, + }, +}; + +module_platform_driver(rockchip_usb_driver); + +MODULE_AUTHOR("Yunzhi Li "); +MODULE_DESCRIPTION("Rockchip USB 2.0 PHY driver"); +MODULE_LICENSE("GPL v2");