From patchwork Sun Jun 21 09:44:38 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Zhong X-Patchwork-Id: 6652281 Return-Path: X-Original-To: patchwork-linux-rockchip@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 09DFBC05AC for ; Sun, 21 Jun 2015 09:45:49 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 2489A206C0 for ; Sun, 21 Jun 2015 09:45:48 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CE54020691 for ; Sun, 21 Jun 2015 09:45:46 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Z6bow-0001iN-11; Sun, 21 Jun 2015 09:45:46 +0000 Received: from mail-qk0-f179.google.com ([209.85.220.179]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Z6boe-0001GW-9e; Sun, 21 Jun 2015 09:45:29 +0000 Received: by qkfe185 with SMTP id e185so85348493qkf.3; Sun, 21 Jun 2015 02:45:06 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=y8ffLG2KJCDfOx6ZB+I8TbPW3DZxQ8pqY1/oTiUaEDg=; b=Inbd+XjLT7k4xxvSGqlANocv3/y2147NuHTLNx4Ln2zvPk4taAuvkkhhqw3HBN2LcV o8Q7Fc+x1AlpNmpeBlPCPSXoDa+ZGVEk379DDB/IeCoAv47epBFSJvr8yhw7loy7Wxvi 4zDoVP1GroxlzEpao7nMf2k87mEyyoUqCyPK0AHOVPLcptiAzbgFkvWPAMOkYSu2zDwX KXN0mCl2i5Y93rAAcZfQAIwV9UJViYgTyJO/NmpdoGCpYu2jaULE6qvau/YXqWe07g0+ 3V+L8YPyKIdE1zS6LjktZ4rkPKVd6s5qkCY+xoudp3cumtEc/lyjeSzc2MDqhJzSSRl5 iEWw== X-Received: by 10.140.134.83 with SMTP id 80mr32906215qhg.28.1434879906581; Sun, 21 Jun 2015 02:45:06 -0700 (PDT) Received: from localhost.localdomain ([199.244.117.124]) by mx.google.com with ESMTPSA id r75sm8371227qkh.6.2015.06.21.02.45.00 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 21 Jun 2015 02:45:05 -0700 (PDT) From: Chris Zhong To: heiko@sntech.de, dianders@chromium.org Subject: [PATCH 1/2] ARM: rockchip: add support holding 24Mhz osc during suspend Date: Sun, 21 Jun 2015 17:44:38 +0800 Message-Id: <1434879879-25162-2-git-send-email-zyw@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1434879879-25162-1-git-send-email-zyw@rock-chips.com> References: <1434879879-25162-1-git-send-email-zyw@rock-chips.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150621_024528_448509_2CBA5227 X-CRM114-Status: GOOD ( 15.23 ) X-Spam-Score: -0.5 (/) Cc: amstan@google.com, Russell King , linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Chris Zhong , sonnyrao@chromium.org, dtor@google.com X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP If we want to wake up system via usb, the 24Mhz osc could not be disabled during suspend, read the usb phy SIDDQ bit to decide whether to switch to 32khz clock-in. Signed-off-by: Chris Zhong --- arch/arm/mach-rockchip/pm.c | 34 +++++++++++++++++++++++++++++++--- 1 file changed, 31 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-rockchip/pm.c b/arch/arm/mach-rockchip/pm.c index b0dcbe2..6d32a82 100644 --- a/arch/arm/mach-rockchip/pm.c +++ b/arch/arm/mach-rockchip/pm.c @@ -29,6 +29,11 @@ #include "pm.h" +#define GRF_UOC0_CON0 0x320 +#define GRF_UOC1_CON0 0x334 +#define GRF_UOC2_CON0 0x348 +#define GRF_SIDDQ BIT(13) + /* These enum are option of low power mode */ enum { ROCKCHIP_ARM_OFF_LOGIC_NORMAL = 0, @@ -45,6 +50,7 @@ static phys_addr_t rk3288_bootram_phy; static struct regmap *pmu_regmap; static struct regmap *sgrf_regmap; +static struct regmap *grf_regmap; static u32 rk3288_pmu_pwr_mode_con; static u32 rk3288_sgrf_soc_con0; @@ -66,9 +72,29 @@ static void rk3288_config_bootdata(void) rkpm_bootdata_l2ctlr = rk3288_l2_config(); } +static bool rk3288_slp_disable_osc(void) +{ + static const u32 reg_offset[] = { GRF_UOC0_CON0, GRF_UOC1_CON0, + GRF_UOC2_CON0 }; + u32 reg, i; + + /* if any usb phy is still on(GRF_SIDDQ==0), that means we need the + * function of usb wakeup, so do not switch to 32khz, since the usb phy + * clk does not connect to 32khz osc*/ + for (i = 0; i < ARRAY_SIZE(reg_offset); i++) { + regmap_read(grf_regmap, reg_offset[i], ®); + if (!(reg & GRF_SIDDQ)) + return false; + } + + return true; +} + static void rk3288_slp_mode_set(int level) { - u32 mode_set, mode_set1; + u32 mode_set, mode_set1, osc_switch_to_32k; + + osc_switch_to_32k = rk3288_slp_disable_osc(); regmap_read(sgrf_regmap, RK3288_SGRF_SOC_CON0, &rk3288_sgrf_soc_con0); @@ -107,11 +133,13 @@ static void rk3288_slp_mode_set(int level) if (level == ROCKCHIP_ARM_OFF_LOGIC_DEEP) { /* arm off, logic deep sleep */ - mode_set |= BIT(PMU_BUS_PD_EN) | + mode_set |= BIT(PMU_BUS_PD_EN) | BIT(PMU_PMU_USE_LF) | BIT(PMU_DDR1IO_RET_EN) | BIT(PMU_DDR0IO_RET_EN) | - BIT(PMU_OSC_24M_DIS) | BIT(PMU_PMU_USE_LF) | BIT(PMU_ALIVE_USE_LF) | BIT(PMU_PLL_PD_EN); + if (osc_switch_to_32k) + mode_set |= BIT(PMU_OSC_24M_DIS); + mode_set1 |= BIT(PMU_CLR_ALIVE) | BIT(PMU_CLR_BUS) | BIT(PMU_CLR_PERI) | BIT(PMU_CLR_DMA); } else {