From patchwork Sun Jun 21 10:00:46 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Zhong X-Patchwork-Id: 6652351 Return-Path: X-Original-To: patchwork-linux-rockchip@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 9A8CBC05AC for ; Sun, 21 Jun 2015 10:01:48 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id BD66120693 for ; Sun, 21 Jun 2015 10:01:47 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E2F3320675 for ; Sun, 21 Jun 2015 10:01:46 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Z6c4Q-00007K-JX; Sun, 21 Jun 2015 10:01:46 +0000 Received: from mail-qk0-f174.google.com ([209.85.220.174]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Z6c4O-0008W8-5k; Sun, 21 Jun 2015 10:01:44 +0000 Received: by qkhu186 with SMTP id u186so85573502qkh.0; Sun, 21 Jun 2015 03:01:22 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=zSRxh6KvF31xhor6MpJSpb1hJfX7rh2/S2xl2HEQUlo=; b=ObWpzaeugEhu+WAuzVC2emnTooay/gFjMuQjhz3jVEZ+L+ufiASxS35Ypa/QWHoS9y ameWHWOCt+JyyFdKseAfv+WaGUAiLgqTZKOBRBsDKBrkhMM2QUvjXFrNqZaSd9EL2ukN sBaT4ByoYrOFL690xVO4HVOhghjxKkyrF+2oChCBWO5tCjzbOxJ18EMeCX1mrMJ28U4s 9Q9L0Mg4oAXQeoVGVcZZywSR/J8KLqpZc7eoBICG/IYOEeJWsPLPbjyChX1o0torh+jk 2pU50Ghm0JB2Jj//ypWSEja7oNlA7gdM06IWMr+jx9jdC72bwOG7N3k8TrvNn/eiS2YE CFFQ== X-Received: by 10.140.21.138 with SMTP id 10mr2825878qgl.47.1434880882520; Sun, 21 Jun 2015 03:01:22 -0700 (PDT) Received: from localhost.localdomain ([199.244.117.124]) by mx.google.com with ESMTPSA id g92sm8648492qgf.20.2015.06.21.03.01.13 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 21 Jun 2015 03:01:21 -0700 (PDT) From: Chris Zhong To: heiko@sntech.de, dianders@chromium.org Subject: [PATCH v2 1/2] ARM: rockchip: add support holding 24Mhz osc during suspend Date: Sun, 21 Jun 2015 18:00:46 +0800 Message-Id: <1434880847-29505-2-git-send-email-zyw@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1434880847-29505-1-git-send-email-zyw@rock-chips.com> References: <1434880847-29505-1-git-send-email-zyw@rock-chips.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150621_030144_290897_8E066458 X-CRM114-Status: GOOD ( 15.89 ) X-Spam-Score: -0.5 (/) Cc: amstan@google.com, Russell King , linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Chris Zhong , sonnyrao@chromium.org, dtor@google.com X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP If we want to wake up system via usb, the 24Mhz osc could not be disabled during suspend, read the usb phy SIDDQ bit to decide whether to switch to 32khz clock-in. Signed-off-by: Chris Zhong Reviewed-by: Douglas Anderson Tested-by: Douglas Anderson --- arch/arm/mach-rockchip/pm.c | 38 ++++++++++++++++++++++++++++++++++++-- 1 file changed, 36 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-rockchip/pm.c b/arch/arm/mach-rockchip/pm.c index b0dcbe2..fda81d3 100644 --- a/arch/arm/mach-rockchip/pm.c +++ b/arch/arm/mach-rockchip/pm.c @@ -29,6 +29,11 @@ #include "pm.h" +#define GRF_UOC0_CON0 0x320 +#define GRF_UOC1_CON0 0x334 +#define GRF_UOC2_CON0 0x348 +#define GRF_SIDDQ BIT(13) + /* These enum are option of low power mode */ enum { ROCKCHIP_ARM_OFF_LOGIC_NORMAL = 0, @@ -45,6 +50,7 @@ static phys_addr_t rk3288_bootram_phy; static struct regmap *pmu_regmap; static struct regmap *sgrf_regmap; +static struct regmap *grf_regmap; static u32 rk3288_pmu_pwr_mode_con; static u32 rk3288_sgrf_soc_con0; @@ -66,9 +72,28 @@ static void rk3288_config_bootdata(void) rkpm_bootdata_l2ctlr = rk3288_l2_config(); } +static bool rk3288_slp_disable_osc(void) +{ + static const u32 reg_offset[] = { GRF_UOC0_CON0, GRF_UOC1_CON0, + GRF_UOC2_CON0 }; + u32 reg, i; + + /* if any usb phy is still on(GRF_SIDDQ==0), that means we need the + * function of usb wakeup, so do not switch to 32khz, since the usb phy + * clk does not connect to 32khz osc*/ + for (i = 0; i < ARRAY_SIZE(reg_offset); i++) { + regmap_read(grf_regmap, reg_offset[i], ®); + if (!(reg & GRF_SIDDQ)) + return false; + } + + return true; +} + static void rk3288_slp_mode_set(int level) { u32 mode_set, mode_set1; + bool osc_switch_to_32k = rk3288_slp_disable_osc(); regmap_read(sgrf_regmap, RK3288_SGRF_SOC_CON0, &rk3288_sgrf_soc_con0); @@ -107,11 +132,13 @@ static void rk3288_slp_mode_set(int level) if (level == ROCKCHIP_ARM_OFF_LOGIC_DEEP) { /* arm off, logic deep sleep */ - mode_set |= BIT(PMU_BUS_PD_EN) | + mode_set |= BIT(PMU_BUS_PD_EN) | BIT(PMU_PMU_USE_LF) | BIT(PMU_DDR1IO_RET_EN) | BIT(PMU_DDR0IO_RET_EN) | - BIT(PMU_OSC_24M_DIS) | BIT(PMU_PMU_USE_LF) | BIT(PMU_ALIVE_USE_LF) | BIT(PMU_PLL_PD_EN); + if (osc_switch_to_32k) + mode_set |= BIT(PMU_OSC_24M_DIS); + mode_set1 |= BIT(PMU_CLR_ALIVE) | BIT(PMU_CLR_BUS) | BIT(PMU_CLR_PERI) | BIT(PMU_CLR_DMA); } else { @@ -193,6 +220,13 @@ static int rk3288_suspend_init(struct device_node *np) return PTR_ERR(pmu_regmap); } + grf_regmap = syscon_regmap_lookup_by_compatible( + "rockchip,rk3288-grf"); + if (IS_ERR(grf_regmap)) { + pr_err("%s: could not find grf regmap\n", __func__); + return PTR_ERR(pmu_regmap); + } + sram_np = of_find_compatible_node(NULL, NULL, "rockchip,rk3288-pmu-sram"); if (!sram_np) {