From patchwork Tue Aug 11 06:15:04 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shunqian Zheng X-Patchwork-Id: 6988741 Return-Path: X-Original-To: patchwork-linux-rockchip@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id A2C649F373 for ; Tue, 11 Aug 2015 06:19:36 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 9ED6820604 for ; Tue, 11 Aug 2015 06:19:35 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8B61620574 for ; Tue, 11 Aug 2015 06:19:34 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZP2uM-0002Qa-9p; Tue, 11 Aug 2015 06:19:34 +0000 Received: from mail-io0-f195.google.com ([209.85.223.195]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZP2uK-0002M6-0u for linux-rockchip@lists.infradead.org; Tue, 11 Aug 2015 06:19:32 +0000 Received: by iodt126 with SMTP id t126so965631iod.3 for ; Mon, 10 Aug 2015 23:19:11 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=LPdqRCu+JbxhlNh8odVek+pQTYrYZfU7YE+7207teYY=; b=S7Ne5E5HSLeaWr8W0gdR4Qk8w24P8VIOc/TYJDorkg9LXD9g7DwfRcw/j1UE6QvVtG /uMTsWufO4ItopW8XiCBIjnATxqSQcrzwfSGSeB9NuVcko6CF/3RAFSknX4uh7rEcD/z w4LYPitr0ZR37caurRI90SAFXQvh3QylTxABPf6YtXDOEWObmya2yB/Xq6Fxu4BgASKO ZjUBtYTbYGMgX8KetmQtz9M/udJH9WsbMFIOV1JjRtH6u4F83n76+7R9w9MoejVaK8Nz /R+7rVmWjiXZR+z6O7fOt57lMJmkZtvoLBmr9y10rH5DLKc1DkLpUQIV7f9obZEjbXBL t7Nw== X-Received: by 10.107.31.77 with SMTP id f74mr31448269iof.8.1439273951097; Mon, 10 Aug 2015 23:19:11 -0700 (PDT) Received: from SHUNQIAN-W530.example.org ([172.245.164.6]) by smtp.gmail.com with ESMTPSA id t66sm909894ioi.32.2015.08.10.23.19.04 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 10 Aug 2015 23:19:10 -0700 (PDT) From: Shunqian Zheng To: gregkh@linuxfoundation.org, srinivas.kandagatla@linaro.org, maxime.ripard@free-electrons.com, heiko@sntech.de, caesar.wang@rock-chips.com Subject: [PATCH v1 3/5] nvmem: rockchip-efuse: implement efuse driver Date: Tue, 11 Aug 2015 14:15:04 +0800 Message-Id: <1439273706-28274-4-git-send-email-zhengsq@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1439273706-28274-1-git-send-email-zhengsq@rock-chips.com> References: <1439273706-28274-1-git-send-email-zhengsq@rock-chips.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150810_231932_153630_8E903652 X-CRM114-Status: GOOD ( 19.83 ) X-Spam-Score: -2.4 (--) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-rockchip@lists.infradead.org, xjq@rock-chips.com, ZhengShunQian , dianders@chromium.org, linux-kernel@vger.kernel.org MIME-Version: 1.0 Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: ZhengShunQian There are some SoC specified values store in eFuse, such as the cpu_leakage and cpu_version, this driver can expose these values to /sys base on nvmem. Signed-off-by: Caesar Wang Signed-off-by: ZhengShunQian --- drivers/nvmem/Kconfig | 10 +++ drivers/nvmem/Makefile | 2 + drivers/nvmem/rockchip-efuse.c | 193 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 205 insertions(+) create mode 100644 drivers/nvmem/rockchip-efuse.c diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig index 8db2978..98f1fac 100644 --- a/drivers/nvmem/Kconfig +++ b/drivers/nvmem/Kconfig @@ -36,4 +36,14 @@ config NVMEM_SUNXI_SID This driver can also be built as a module. If so, the module will be called nvmem_sunxi_sid. +config ROCKCHIP_EFUSE + tristate "Rockchip eFuse Support" + depends on ARCH_ROCKCHIP || COMPILE_TEST + help + This is a simple drive to dump specified values of Rockchip SoC + from eFuse, such as cpu-leakage. + + This driver can also be built as a module. If so, the module + will be called nvmem_rockchip_efuse. + endif diff --git a/drivers/nvmem/Makefile b/drivers/nvmem/Makefile index 4328b93..093a528 100644 --- a/drivers/nvmem/Makefile +++ b/drivers/nvmem/Makefile @@ -10,3 +10,5 @@ obj-$(CONFIG_QCOM_QFPROM) += nvmem_qfprom.o nvmem_qfprom-y := qfprom.o obj-$(CONFIG_NVMEM_SUNXI_SID) += nvmem_sunxi_sid.o nvmem_sunxi_sid-y := sunxi_sid.o +obj-$(CONFIG_ROCKCHIP_EFUSE) += nvmem_rockchip_efuse.o +nvmem_rockchip_efuse-y := rockchip-efuse.o diff --git a/drivers/nvmem/rockchip-efuse.c b/drivers/nvmem/rockchip-efuse.c new file mode 100644 index 0000000..9d1e2e0 --- /dev/null +++ b/drivers/nvmem/rockchip-efuse.c @@ -0,0 +1,193 @@ +/* + * Rockchip eFuse Driver + * + * Copyright (c) 2015 Rockchip Electronics Co. Ltd. + * Author: Caesar Wang + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define EFUSE_A_SHIFT 6 +#define EFUSE_A_MASK 0x3ff +#define EFUSE_PGENB BIT(3) +#define EFUSE_LOAD BIT(2) +#define EFUSE_STROBE BIT(1) +#define EFUSE_CSB BIT(0) + +#define REG_EFUSE_CTRL 0x0000 +#define REG_EFUSE_DOUT 0x0004 + +struct rockchip_efuse_context { + struct device *dev; + void __iomem *base; + struct clk *efuse_clk; +}; + +static int rockchip_efuse_write(void *context, const void *data, size_t count) +{ + /* Nothing TBD, Read-Only */ + return 0; +} + +static int rockchip_efuse_read(void *context, + const void *reg, size_t reg_size, + void *val, size_t val_size) +{ + unsigned int offset = *(u32 *)reg; + struct rockchip_efuse_context *_context = context; + void __iomem *base = _context->base; + struct clk *clk = _context->efuse_clk; + u8 *buf = val; + int ret; + + ret = clk_prepare(clk); + if (ret < 0) { + dev_err(_context->dev, "failed to prepare efuse clk\n"); + return ret; + } + ret = clk_enable(clk); + if (ret < 0) { + dev_err(_context->dev, "failed to enable efuse clk\n"); + clk_unprepare(clk); + return ret; + } + + writel(EFUSE_LOAD | EFUSE_PGENB, base + REG_EFUSE_CTRL); + udelay(1); + while (val_size) { + writel(readl(base + REG_EFUSE_CTRL) & + (~(EFUSE_A_MASK << EFUSE_A_SHIFT)), + base + REG_EFUSE_CTRL); + writel(readl(base + REG_EFUSE_CTRL) | + ((offset & EFUSE_A_MASK) << EFUSE_A_SHIFT), + base + REG_EFUSE_CTRL); + udelay(1); + writel(readl(base + REG_EFUSE_CTRL) | + EFUSE_STROBE, base + REG_EFUSE_CTRL); + udelay(1); + *buf++ = readb(base + REG_EFUSE_DOUT); + writel(readl(base + REG_EFUSE_CTRL) & + (~EFUSE_STROBE), base + REG_EFUSE_CTRL); + udelay(1); + + val_size -= 1; + offset += 1; + } + + /* Switch to standby mode */ + writel(EFUSE_PGENB | EFUSE_CSB, base + REG_EFUSE_CTRL); + + clk_disable(clk); + clk_unprepare(clk); + + return 0; +} + +static struct regmap_bus rockchip_efuse_bus = { + .read = rockchip_efuse_read, + .write = rockchip_efuse_write, + .reg_format_endian_default = REGMAP_ENDIAN_NATIVE, + .val_format_endian_default = REGMAP_ENDIAN_NATIVE, +}; + +struct regmap_config rockchip_efuse_regmap_config = { + .reg_bits = 32, + .reg_stride = 1, + .val_bits = 8, +}; + +static struct nvmem_config econfig = { + .name = "rockchip-efuse", + .owner = THIS_MODULE, + .read_only = true, +}; + +static const struct of_device_id rockchip_efuse_match[] = { + { .compatible = "rockchip,rockchip-efuse",}, + { /* sentinel */}, +}; +MODULE_DEVICE_TABLE(of, rockchip_efuse_match); + +int rockchip_efuse_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct resource *res; + struct nvmem_device *nvmem; + struct regmap *regmap; + void __iomem *base; + struct clk *clk; + struct rockchip_efuse_context *context; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + base = devm_ioremap_resource(dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + context = devm_kzalloc(dev, sizeof(struct rockchip_efuse_context), + GFP_KERNEL); + if (IS_ERR(context)) + return PTR_ERR(context); + + clk = devm_clk_get(dev, "pclk_efuse"); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + context->dev = dev; + context->base = base; + context->efuse_clk = clk; + + rockchip_efuse_regmap_config.max_register = resource_size(res) - 1; + + regmap = devm_regmap_init(dev, &rockchip_efuse_bus, + context, &rockchip_efuse_regmap_config); + if (IS_ERR(regmap)) { + dev_err(dev, "regmap init failed\n"); + return PTR_ERR(regmap); + } + econfig.dev = dev; + nvmem = nvmem_register(&econfig); + if (IS_ERR(nvmem)) + return PTR_ERR(nvmem); + + platform_set_drvdata(pdev, nvmem); + + return 0; +} + +int rockchip_efuse_remove(struct platform_device *pdev) +{ + struct nvmem_device *nvmem = platform_get_drvdata(pdev); + + return nvmem_unregister(nvmem); +} + +static struct platform_driver rockchip_efuse_driver = { + .probe = rockchip_efuse_probe, + .remove = rockchip_efuse_remove, + .driver = { + .name = "rockchip-efuse", + .of_match_table = rockchip_efuse_match, + }, +}; + +module_platform_driver(rockchip_efuse_driver); +MODULE_DESCRIPTION("rockchip_efuse driver"); +MODULE_LICENSE("GPL v2");