From patchwork Thu Sep 17 10:38:06 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: zhengxing X-Patchwork-Id: 7205971 Return-Path: X-Original-To: patchwork-linux-rockchip@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id E44D99F39B for ; Thu, 17 Sep 2015 10:38:51 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 04AA820690 for ; Thu, 17 Sep 2015 10:38:51 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0DDD520641 for ; Thu, 17 Sep 2015 10:38:50 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZcWaX-0007eF-8S; Thu, 17 Sep 2015 10:38:49 +0000 Received: from regular1.263xmail.com ([211.150.99.137]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZcWaL-0007On-Lp; Thu, 17 Sep 2015 10:38:39 +0000 Received: from zhengxing?rock-chips.com (unknown [192.168.167.228]) by regular1.263xmail.com (Postfix) with SMTP id A45EC9018; Thu, 17 Sep 2015 18:38:07 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 X-ADDR-CHECKED: 0 Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.263.net (Postfix) with ESMTP id 5F8FB455; Thu, 17 Sep 2015 18:38:06 +0800 (CST) X-RL-SENDER: zhengxing@rock-chips.com X-FST-TO: heiko@sntech.de X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: zhengxing@rock-chips.com X-UNIQUE-TAG: <7e558006c113f5080e48f982de7d7e12> X-ATTACHMENT-NUM: 0 X-SENDER: zhengxing@rock-chips.com X-DNS-TYPE: 0 Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.263.net (Postfix) whith ESMTP id 8931KAIFRV; Thu, 17 Sep 2015 18:38:07 +0800 (CST) From: Xing Zheng To: heiko@sntech.de Subject: [PATCH v2 8/9] ARM: rockchip: add support smp for rk3036 Date: Thu, 17 Sep 2015 18:38:06 +0800 Message-Id: <1442486286-1873-1-git-send-email-zhengxing@rock-chips.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1442478540-15068-1-git-send-email-zhengxing@rock-chips.com> References: <1442478540-15068-1-git-send-email-zhengxing@rock-chips.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150917_033839_387856_8D1DAFBC X-CRM114-Status: GOOD ( 13.16 ) X-Spam-Score: -1.9 (-) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-rockchip@lists.infradead.org, zhengxing@rock-chips.com, linux@arm.linux.org.uk, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The rk3036 is dual-core soc, we can use this patch to enable cpu1 enter boot secondary, and hotplug(online/offline). Signed-off-by: Xing Zheng --- Changes in v2: None arch/arm/mach-rockchip/platsmp.c | 121 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 121 insertions(+) diff --git a/arch/arm/mach-rockchip/platsmp.c b/arch/arm/mach-rockchip/platsmp.c index 3e7a4b7..14218eb 100644 --- a/arch/arm/mach-rockchip/platsmp.c +++ b/arch/arm/mach-rockchip/platsmp.c @@ -34,6 +34,8 @@ static void __iomem *scu_base_addr; static void __iomem *sram_base_addr; +static void __iomem *cru_base_addr; + static int ncores; #define PMU_PWRDN_CON 0x08 @@ -41,6 +43,8 @@ static int ncores; #define PMU_PWRDN_SCU 4 +#define RK3036_SOFTRST_CON(x) ((x) * 0x4 + 0x110) + static struct regmap *pmu; static int pmu_power_domain_is_on(int pd) @@ -184,6 +188,7 @@ static int __init rockchip_smp_prepare_sram(struct device_node *node) } rsize = resource_size(&res); + if (rsize < trampoline_sz) { pr_err("%s: reserved block with size 0x%x is to small for trampoline size 0x%x\n", __func__, rsize, trampoline_sz); @@ -350,3 +355,119 @@ static struct smp_operations rockchip_smp_ops __initdata = { }; CPU_METHOD_OF_DECLARE(rk3066_smp, "rockchip,rk3066-smp", &rockchip_smp_ops); + +/* for rk3036 */ + +static int rk3036_set_power_domain(int pd, bool on) +{ + /* there are 2cpus on rk3036 soc, we just need to be care cpu1 */ + if (pd != 1) + return 0; + + if (on) + writel_relaxed(0x20000, cru_base_addr + RK3036_SOFTRST_CON(0)); + else + writel_relaxed(0x20002, cru_base_addr + RK3036_SOFTRST_CON(0)); + + dsb(); + + return 0; +} + +static void __init rk3036_smp_prepare_cpus(unsigned int max_cpus) +{ + struct device_node *node; + unsigned int l2ctlr; + unsigned int i, cpu; + + /* get cru_base_addr */ + node = of_find_compatible_node(NULL, NULL, "rockchip,rk3036-cru"); + if (!node) { + pr_err("%s: could not find cru dt node\n", __func__); + return; + } + + cru_base_addr = of_iomap(node, 0); + if (!cru_base_addr) { + pr_err("%s: could not map cru registers\n", __func__); + return; + } + + /* get sram_base_addr */ + node = of_find_compatible_node(NULL, NULL, "rockchip,rk3036-smp-sram"); + if (!node) { + pr_err("%s: could not find sram dt node\n", __func__); + return; + } + + sram_base_addr = of_iomap(node, 0); + if (!sram_base_addr) { + pr_err("%s: could not map sram registers\n", __func__); + return; + } + + /* get ncores */ + asm ("mrc p15, 1, %0, c9, c0, 2\n" : "=r" (l2ctlr)); + ncores = ((l2ctlr >> 24) & 0x3) + 1; + cpu = MPIDR_AFFINITY_LEVEL(read_cpuid_mpidr(), 0); + + /* Make sure that all cores except the first are really off */ + for (i = 1; i < ncores; i++) + rk3036_set_power_domain(0 + i, false); +} + +static int rk3036_boot_secondary(unsigned int cpu, struct task_struct *idle) +{ + if (cpu >= ncores) { + pr_err("%s: cpu %d outside maximum number of cpus %d\n", + __func__, cpu, ncores); + return -ENXIO; + } + + /* start the core */ + rk3036_set_power_domain(0 + cpu, true); + + /* + * We need to wait a moment after soft reset CPUx on rk3036, + * otherwise, CPUx will startup failed. + */ + udelay(10); + writel(virt_to_phys(secondary_startup), sram_base_addr + 8); + writel(0xDEADBEAF, sram_base_addr + 4); + dsb_sev(); + + return 0; +} + +#ifdef CONFIG_HOTPLUG_CPU +static int rk3066_cpu_kill(unsigned int cpu) +{ + /* + * We need a delay here to ensure that the dying CPU can finish + * executing v7_coherency_exit() and reach the WFI/WFE state + * prior to having the power domain disabled. + */ + mdelay(1); + + rk3036_set_power_domain(0 + cpu, false); + + return 1; +} + +static void rk3066_cpu_die(unsigned int cpu) +{ + v7_exit_coherency_flush(louis); + while (1) + cpu_do_idle(); +} +#endif + +static struct smp_operations rk3036_smp_ops __initdata = { + .smp_prepare_cpus = rk3036_smp_prepare_cpus, + .smp_boot_secondary = rk3036_boot_secondary, +#ifdef CONFIG_HOTPLUG_CPU + .cpu_kill = rk3066_cpu_kill, + .cpu_die = rk3066_cpu_die, +#endif +}; +CPU_METHOD_OF_DECLARE(rk3036_smp, "rockchip,rk3036-smp", &rk3036_smp_ops);