From patchwork Tue Sep 29 02:13:51 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: zhengxing X-Patchwork-Id: 7281971 Return-Path: X-Original-To: patchwork-linux-rockchip@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 26D0B9F32B for ; Tue, 29 Sep 2015 02:15:45 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 3616820306 for ; Tue, 29 Sep 2015 02:15:44 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8A5AA20718 for ; Tue, 29 Sep 2015 02:15:42 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZgkSE-0004s2-9u; Tue, 29 Sep 2015 02:15:42 +0000 Received: from m50-110.126.com ([123.125.50.110]) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZgkRV-0003XB-Rb; Tue, 29 Sep 2015 02:14:58 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=126.com; s=s110527; h=From:Subject:Date:Message-Id; bh=VL0wixpRc13Hs0ZU6Z vzYH+uFfHv68+a2txRpT7vat8=; b=SZWgGVfhZJLkx/pacxNgUwFkReaA6eYanx QjZKFOXb6Ez27ofKoN13o4PKSQHojG77YSPMZ8cPW3qftexZ9miQZh0JhRhZ9PHv A244iNiLIjcfouHAiEAHJLbBdstC3UyHVJoLFHwvDALLDWhym5XRtQLA3vep7aKN fPjxdaaOE= Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp4 (Coremail) with SMTP id jdKowAAHNTbm8wlWsm1UAw--.42159S8; Tue, 29 Sep 2015 10:14:06 +0800 (CST) From: Xing Zheng To: heiko@sntech.de Subject: [PATCH v3 6/8] ARM: rockchip: add support smp for rk3036 Date: Tue, 29 Sep 2015 10:13:51 +0800 Message-Id: <1443492833-15630-7-git-send-email-zhengxing@rock-chips.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1443492833-15630-1-git-send-email-zhengxing@rock-chips.com> References: <1443492833-15630-1-git-send-email-zhengxing@rock-chips.com> X-CM-TRANSID: jdKowAAHNTbm8wlWsm1UAw--.42159S8 X-Coremail-Antispam: 1Uf129KBjvJXoWxZw4fKF4xKFWDGFWkCrWUXFb_yoWruF45pw 47Gry5XrZ7GFyIkw4ftFZ5Jr4F9rn5tF4UX39akF1Dtr4fX3s8Gr48WF1YkFyrGryIgayF yr42yF4ruFZFvFDanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x07jPvtAUUUUU= X-Originating-IP: [58.22.7.114] X-CM-SenderInfo: hdfj65a6rslhhfrp/1tbidA6E-VPgrwBAwAAAsf X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150928_191458_326275_245C16F3 X-CRM114-Status: GOOD ( 15.20 ) X-Spam-Score: -1.7 (-) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-rockchip@lists.infradead.org, Russell King , linux-arm-kernel@lists.infradead.org, Xing Zheng , linux-kernel@vger.kernel.org MIME-Version: 1.0 Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The rk3036 is dual-core soc, we can use this patch to enable cpu1 enter boot secondary, and hotplug(online/offline). Signed-off-by: Xing Zheng Reviewed-by: Heiko Stuebner --- Changes in v3: None arch/arm/mach-rockchip/platsmp.c | 142 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 142 insertions(+) diff --git a/arch/arm/mach-rockchip/platsmp.c b/arch/arm/mach-rockchip/platsmp.c index 3e7a4b7..7864bf3 100644 --- a/arch/arm/mach-rockchip/platsmp.c +++ b/arch/arm/mach-rockchip/platsmp.c @@ -34,6 +34,8 @@ static void __iomem *scu_base_addr; static void __iomem *sram_base_addr; +static void __iomem *cru_base_addr; + static int ncores; #define PMU_PWRDN_CON 0x08 @@ -41,6 +43,8 @@ static int ncores; #define PMU_PWRDN_SCU 4 +#define RK3036_SOFTRST_CON(x) ((x) * 0x4 + 0x110) + static struct regmap *pmu; static int pmu_power_domain_is_on(int pd) @@ -350,3 +354,141 @@ static struct smp_operations rockchip_smp_ops __initdata = { }; CPU_METHOD_OF_DECLARE(rk3066_smp, "rockchip,rk3066-smp", &rockchip_smp_ops); + +/* for RK3036 */ + +static int rk3036_set_power_domain(int pd, bool on) +{ + struct reset_control *rstc = rockchip_get_core_reset(pd); + u32 val; + + /* there are 2cpus on rk3036 soc, we just need to be care cpu1 */ + if (pd != 1) + return 0; + + if (IS_ERR(rstc) && read_cpuid_part() != ARM_CPU_PART_CORTEX_A9) { + pr_err("%s: could not get reset control for core %d\n", + __func__, pd); + return PTR_ERR(rstc); + } + + /* + * We need to soft reset the cpu when we turn off the cpu power domain, + * or else the active processors might be stalled when the individual + * processor is powered down. + */ + if (!IS_ERR(rstc) && !on) + reset_control_assert(rstc); + + val = (on) ? 0 : 1; + val = (val << pd) | BIT(pd + 16); + writel_relaxed(val, cru_base_addr + RK3036_SOFTRST_CON(0)); + + dsb(); + + if (!IS_ERR(rstc)) { + if (on) + reset_control_deassert(rstc); + reset_control_put(rstc); + } + + return 0; +} + +static void __init rk3036_smp_prepare_cpus(unsigned int max_cpus) +{ + struct device_node *node; + unsigned int l2ctlr; + unsigned int i, cpu; + + /* get cru_base_addr */ + node = of_find_compatible_node(NULL, NULL, "rockchip,rk3036-cru"); + if (!node) { + pr_err("%s: could not find cru dt node\n", __func__); + return; + } + + cru_base_addr = of_iomap(node, 0); + if (!cru_base_addr) { + pr_err("%s: could not map cru registers\n", __func__); + return; + } + + /* get sram_base_addr */ + node = of_find_compatible_node(NULL, NULL, "rockchip,rk3036-smp-sram"); + if (!node) { + pr_err("%s: could not find sram dt node\n", __func__); + return; + } + + sram_base_addr = of_iomap(node, 0); + if (!sram_base_addr) { + pr_err("%s: could not map sram registers\n", __func__); + return; + } + + /* get ncores */ + asm ("mrc p15, 1, %0, c9, c0, 2\n" : "=r" (l2ctlr)); + ncores = ((l2ctlr >> 24) & 0x3) + 1; + cpu = MPIDR_AFFINITY_LEVEL(read_cpuid_mpidr(), 0); + + /* Make sure that all cores except the first are really off */ + for (i = 1; i < ncores; i++) + rk3036_set_power_domain(0 + i, false); +} + +static int rk3036_boot_secondary(unsigned int cpu, struct task_struct *idle) +{ + if (cpu >= ncores) { + pr_err("%s: cpu %d outside maximum number of cpus %d\n", + __func__, cpu, ncores); + return -ENXIO; + } + + /* start the core */ + rk3036_set_power_domain(0 + cpu, true); + + /* + * We need to wait a moment after soft reset CPUx on rk3036, + * otherwise, CPUx will startup failed. + */ + udelay(10); + writel(virt_to_phys(secondary_startup), sram_base_addr + 8); + writel(0xDEADBEAF, sram_base_addr + 4); + dsb_sev(); + + return 0; +} + +#ifdef CONFIG_HOTPLUG_CPU +static int rk3066_cpu_kill(unsigned int cpu) +{ + /* + * We need a delay here to ensure that the dying CPU can finish + * executing v7_coherency_exit() and reach the WFI/WFE state + * prior to having the power domain disabled. + */ + mdelay(1); + + rk3036_set_power_domain(0 + cpu, false); + + return 1; +} + +static void rk3066_cpu_die(unsigned int cpu) +{ + v7_exit_coherency_flush(louis); + while (1) + cpu_do_idle(); +} +#endif + +static struct smp_operations rk3036_smp_ops __initdata = { + .smp_prepare_cpus = rk3036_smp_prepare_cpus, + .smp_boot_secondary = rk3036_boot_secondary, +#ifdef CONFIG_HOTPLUG_CPU + .cpu_kill = rk3066_cpu_kill, + .cpu_die = rk3066_cpu_die, +#endif +}; +CPU_METHOD_OF_DECLARE(rk3036_smp, "rockchip,rk3036-smp", &rk3036_smp_ops);