From patchwork Thu Nov 19 03:35:23 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Zhong X-Patchwork-Id: 7654311 Return-Path: X-Original-To: patchwork-linux-rockchip@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id A32E9BF90C for ; Thu, 19 Nov 2015 03:38:21 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id BDEE6204D5 for ; Thu, 19 Nov 2015 03:38:19 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D165A204AD for ; Thu, 19 Nov 2015 03:38:18 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZzG38-0004pO-5k; Thu, 19 Nov 2015 03:38:18 +0000 Received: from mail-ig0-f169.google.com ([209.85.213.169]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZzG2r-0004QY-WD for linux-rockchip@lists.infradead.org; Thu, 19 Nov 2015 03:38:04 +0000 Received: by igcto18 with SMTP id to18so54206285igc.0 for ; Wed, 18 Nov 2015 19:37:41 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=1sHPhX2wxsbaFluLDukB81iGs3uTNIdI2HgGm5/q7Pg=; b=SXovuAJrir9EbVkpx6P7NcXXs/8OXRYqX3sih+jECM0IEgqsK9LW3kjiQpZlHQy6sA hP7EdhLogtxhmJ+NMf7dIc+8xefLMyUEs/AAUp6g3+A9v2JHoUy8SMwGqTXCtE0rLYeM u16wygWvkcEYqHQuxCJPPOTwYBMgm00uhqOoTFYxWRwP8mccyyRXP+ibM6eLjzkQOcyQ WZrXVpvH1KcTJMlQC+lk5uqFRY9tRF3kGQBkdm3+/zfQL5G819TeLz/3AKlw2yK8BRgZ s7KabMziWYF9uRJabNIdUuLJix+ECa5M9RcWcc+Zk28te3YKNuvXDqR5Z+Vi1dB3Kg8t NSAg== X-Received: by 10.50.155.106 with SMTP id vv10mr11607967igb.55.1447904260846; Wed, 18 Nov 2015 19:37:40 -0800 (PST) Received: from localhost.localdomain ([45.74.60.49]) by smtp.gmail.com with ESMTPSA id n3sm11392131iga.0.2015.11.18.19.37.32 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 18 Nov 2015 19:37:39 -0800 (PST) From: Chris Zhong To: heiko@sntech.de, linux-rockchip@lists.infradead.org, Mark Yao Subject: [PATCH v3 05/12] Documentation: dt-bindings: Add bindings for Synopsys DW MIPI DSI DRM bridge driver Date: Thu, 19 Nov 2015 11:35:23 +0800 Message-Id: <1447904131-29328-6-git-send-email-zyw@rock-chips.com> X-Mailer: git-send-email 2.6.3 In-Reply-To: <1447904131-29328-1-git-send-email-zyw@rock-chips.com> References: <1447904131-29328-1-git-send-email-zyw@rock-chips.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151118_193802_398988_E613AA8E X-CRM114-Status: GOOD ( 14.76 ) X-Spam-Score: -2.2 (--) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, Pawel Moll , Ian Campbell , linux-kernel@vger.kernel.org, Rob Herring , Kumar Gala , Chris Zhong , Liu Ying MIME-Version: 1.0 Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Liu Ying This patch adds device tree bindings for Synopsys DesignWare MIPI DSI host controller DRM bridge driver. Signed-off-by: Liu Ying Signed-off-by: Chris Zhong --- Changes in v3: move the dw_mipi_dsi.txt to Documentation/devicetree/bindings/display/bridge Changes in v2: None .../bindings/display/bridge/dw_mipi_dsi.txt | 76 ++++++++++++++++++++++ 1 file changed, 76 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt diff --git a/Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt b/Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt new file mode 100644 index 0000000..0e5c140 --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt @@ -0,0 +1,76 @@ +Device-Tree bindings for Synopsys DesignWare MIPI DSI host controller + +The controller is a digital core that implements all protocol functions +defined in the MIPI DSI specification, providing an interface between +the system and the MIPI DPHY, and allowing communication with a MIPI DSI +compliant display. + +Required properties: + - #address-cells: Should be <1>. + - #size-cells: Should be <0>. + - compatible: The first compatible string should be "fsl,imx6q-mipi-dsi" + for i.MX6q/sdl SoCs. For other SoCs, please refer to their specific + device tree binding documentations. A common compatible string + "snps,dw-mipi-dsi" should be appended for all SoCs. + - reg: Represent the physical address range of the controller. + - interrupts: Represent the controller's interrupt to the CPU(s). + - clocks, clock-names: Phandles to the controller's pll reference + clock(ref), configuration clock(cfg) and APB clock(pclk), as + described in [1]. + +For more required properties, please refer to relevant device tree binding +documentations which describe the controller embedded in specific SoCs. + +Required sub-nodes: + - A node to represent a DSI peripheral as described in [2]. + +For more required sub-nodes, please refer to relevant device tree binding +documentations which describe the controller embedded in specific SoCs. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt +[2] Documentation/devicetree/bindings/display/mipi-dsi-bus.txt + +example: + gpr: iomuxc-gpr@020e0000 { + /* ... */ + }; + + mipi_dsi: mipi@021e0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6q-mipi-dsi", "snps,dw-mipi-dsi"; + reg = <0x021e0000 0x4000>; + interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>; + gpr = <&gpr>; + clocks = <&clks IMX6QDL_CLK_MIPI_CORE_CFG>, + <&clks IMX6QDL_CLK_MIPI_CORE_CFG>, + <&clks IMX6QDL_CLK_MIPI_IPG>; + clock-names = "ref", "cfg", "pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mipi_mux_0: endpoint { + remote-endpoint = <&ipu1_di0_mipi>; + }; + }; + + port@1 { + reg = <1>; + + mipi_mux_1: endpoint { + remote-endpoint = <&ipu1_di1_mipi>; + }; + }; + }; + + panel { + compatible = "truly,tft480800-16-e-dsi"; + reg = <0>; + /* ... */ + }; + };