From patchwork Thu Dec 17 03:37:02 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: yao mark X-Patchwork-Id: 7869151 Return-Path: X-Original-To: patchwork-linux-rockchip@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 3FC19BEEE5 for ; Thu, 17 Dec 2015 03:39:16 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 3E804203B8 for ; Thu, 17 Dec 2015 03:39:15 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 324BD203C0 for ; Thu, 17 Dec 2015 03:39:14 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1a9PPN-0004Zz-RP; Thu, 17 Dec 2015 03:39:13 +0000 Received: from regular1.263xmail.com ([211.150.99.137]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1a9POw-00044a-2t; Thu, 17 Dec 2015 03:38:50 +0000 Received: from mark.yao?rock-chips.com (unknown [192.168.167.87]) by regular1.263xmail.com (Postfix) with SMTP id 314C0B940; Thu, 17 Dec 2015 11:38:16 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 X-ADDR-CHECKED: 0 Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.263.net (Postfix) with ESMTP id E2B4E4448; Thu, 17 Dec 2015 11:38:15 +0800 (CST) X-RL-SENDER: mark.yao@rock-chips.com X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: mark.yao@rock-chips.com X-UNIQUE-TAG: <3cfd2792db429183a51417696410c44d> X-ATTACHMENT-NUM: 0 X-SENDER: yzq@rock-chips.com X-DNS-TYPE: 0 Received: from unknown (unknown [58.22.7.114]) by smtp.263.net (Postfix) whith SMTP id 6502O6HTLR; Thu, 17 Dec 2015 11:38:16 +0800 (CST) From: Mark Yao To: David Airlie , Heiko Stuebner , dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/6] drm/rockchip: vop: move interrupt registers into vop_data Date: Thu, 17 Dec 2015 11:37:02 +0800 Message-Id: <1450323426-32109-3-git-send-email-mark.yao@rock-chips.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1450323426-32109-1-git-send-email-mark.yao@rock-chips.com> References: <1450323426-32109-1-git-send-email-mark.yao@rock-chips.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151216_193848_580269_A0FFB865 X-CRM114-Status: GOOD ( 12.56 ) X-Spam-Score: -1.9 (-) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Yao MIME-Version: 1.0 Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Move interrupt registers into vop_data, so it can use at multi-vop driver Signed-off-by: Mark Yao --- drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 81 +++++++++++++++++++++++---- 1 file changed, 69 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c index dcb1396..7674bdc 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c @@ -48,6 +48,8 @@ #define REG_SET(x, base, reg, v, mode) \ __REG_SET_##mode(x, base + reg.offset, reg.mask, reg.shift, v) +#define REG_SET_MASK(x, base, reg, v, mode) \ + __REG_SET_##mode(x, base + reg.offset, reg.mask, reg.shift, v) #define VOP_WIN_SET(x, win, name, v) \ REG_SET(x, win->base, win->phy->name, v, RELAXED) @@ -56,6 +58,23 @@ #define VOP_CTRL_SET(x, name, v) \ REG_SET(x, 0, (x)->data->ctrl->name, v, NORMAL) +#define VOP_INTR_GET(vop, name) \ + vop_read_reg(vop, 0, &vop->data->ctrl->name) + +#define VOP_INTR_SET(vop, name, v) \ + REG_SET(vop, 0, vop->data->intr->name, v, NORMAL) +#define VOP_INTR_SET_TYPE(vop, name, type, v) \ + do { \ + int i, reg = 0; \ + for (i = 0; i < vop->data->intr->nintrs; i++) { \ + if (vop->data->intr->intrs[i] & type) \ + reg |= (v) << i; \ + } \ + VOP_INTR_SET(vop, name, reg); \ + } while (0) +#define VOP_INTR_GET_TYPE(vop, name, type) \ + vop_get_intr_type(vop, &vop->data->intr->name, type) + #define VOP_WIN_GET(x, win, name) \ vop_read_reg(x, win->base, &win->phy->name) @@ -168,6 +187,13 @@ struct vop_ctrl { struct vop_reg cfg_done; }; +struct vop_intr { + const int *intrs; + uint32_t nintrs; + struct vop_reg enable; + struct vop_reg clear; + struct vop_reg status; +}; struct vop_scl_regs { struct vop_reg cbcr_vsd_mode; struct vop_reg cbcr_vsu_mode; @@ -227,6 +253,7 @@ struct vop_data { const struct vop_reg_data *init_table; unsigned int table_size; const struct vop_ctrl *ctrl; + const struct vop_intr *intr; const struct vop_win_data *win; unsigned int win_size; }; @@ -364,8 +391,24 @@ static const struct vop_win_data rk3288_vop_win_data[] = { { .base = 0x50, .phy = &win23_data, .type = DRM_PLANE_TYPE_CURSOR }, }; +static const int rk3288_vop_intrs[] = { + DSP_HOLD_VALID_INTR, + FS_INTR, + LINE_FLAG_INTR, + BUS_ERROR_INTR, +}; + +static const struct vop_intr rk3288_vop_intr = { + .intrs = rk3288_vop_intrs, + .nintrs = ARRAY_SIZE(rk3288_vop_intrs), + .status = VOP_REG(INTR_CTRL0, 0xf, 0), + .enable = VOP_REG(INTR_CTRL0, 0xf, 4), + .clear = VOP_REG(INTR_CTRL0, 0xf, 8), +}; + static const struct vop_data rk3288_vop = { .init_table = vop_init_reg_table, + .intr = &rk3288_vop_intr, .table_size = ARRAY_SIZE(vop_init_reg_table), .ctrl = &ctrl_data, .win = rk3288_vop_win_data, @@ -420,6 +463,20 @@ static inline void vop_mask_write_relaxed(struct vop *vop, uint32_t offset, } } +static inline uint32_t vop_get_intr_type(struct vop *vop, + const struct vop_reg *reg, int type) +{ + uint32_t i, ret = 0; + uint32_t regs = vop_read_reg(vop, 0, reg); + + for (i = 0; i < vop->data->intr->nintrs; i++) { + if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i)) + ret |= vop->data->intr->intrs[i]; + } + + return ret; +} + static inline void vop_cfg_done(struct vop *vop) { VOP_CTRL_SET(vop, cfg_done, 1); @@ -616,8 +673,7 @@ static void vop_dsp_hold_valid_irq_enable(struct vop *vop) spin_lock_irqsave(&vop->irq_lock, flags); - vop_mask_write(vop, INTR_CTRL0, DSP_HOLD_VALID_INTR_MASK, - DSP_HOLD_VALID_INTR_EN(1)); + VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1); spin_unlock_irqrestore(&vop->irq_lock, flags); } @@ -631,8 +687,7 @@ static void vop_dsp_hold_valid_irq_disable(struct vop *vop) spin_lock_irqsave(&vop->irq_lock, flags); - vop_mask_write(vop, INTR_CTRL0, DSP_HOLD_VALID_INTR_MASK, - DSP_HOLD_VALID_INTR_EN(0)); + VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0); spin_unlock_irqrestore(&vop->irq_lock, flags); } @@ -1051,7 +1106,7 @@ static int vop_crtc_enable_vblank(struct drm_crtc *crtc) spin_lock_irqsave(&vop->irq_lock, flags); - vop_mask_write(vop, INTR_CTRL0, FS_INTR_MASK, FS_INTR_EN(1)); + VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1); spin_unlock_irqrestore(&vop->irq_lock, flags); @@ -1067,7 +1122,9 @@ static void vop_crtc_disable_vblank(struct drm_crtc *crtc) return; spin_lock_irqsave(&vop->irq_lock, flags); - vop_mask_write(vop, INTR_CTRL0, FS_INTR_MASK, FS_INTR_EN(0)); + + VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0); + spin_unlock_irqrestore(&vop->irq_lock, flags); } @@ -1263,21 +1320,21 @@ static irqreturn_t vop_isr(int irq, void *data) { struct vop *vop = data; struct drm_crtc *crtc = &vop->crtc; - uint32_t intr0_reg, active_irqs; + uint32_t active_irqs; unsigned long flags; int ret = IRQ_NONE; /* - * INTR_CTRL0 register has interrupt status, enable and clear bits, we + * interrupt register has interrupt status, enable and clear bits, we * must hold irq_lock to avoid a race with enable/disable_vblank(). */ spin_lock_irqsave(&vop->irq_lock, flags); - intr0_reg = vop_readl(vop, INTR_CTRL0); - active_irqs = intr0_reg & INTR_MASK; + + active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK); /* Clear all active interrupt sources */ if (active_irqs) - vop_writel(vop, INTR_CTRL0, - intr0_reg | (active_irqs << INTR_CLR_SHIFT)); + VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1); + spin_unlock_irqrestore(&vop->irq_lock, flags); /* This is expected for vop iommu irqs, since the irq is shared */