From patchwork Thu Dec 17 03:37:04 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: yao mark X-Patchwork-Id: 7869141 Return-Path: X-Original-To: patchwork-linux-rockchip@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 66A8F9F387 for ; Thu, 17 Dec 2015 03:39:14 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 63976203B8 for ; Thu, 17 Dec 2015 03:39:13 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 67534202B8 for ; Thu, 17 Dec 2015 03:39:12 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1a9PPM-0004Xa-0B; Thu, 17 Dec 2015 03:39:12 +0000 Received: from regular1.263xmail.com ([211.150.99.138]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1a9POs-00046I-A2; Thu, 17 Dec 2015 03:38:45 +0000 Received: from mark.yao?rock-chips.com (unknown [192.168.167.87]) by regular1.263xmail.com (Postfix) with SMTP id 991DD51D3; Thu, 17 Dec 2015 11:38:18 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 X-ADDR-CHECKED: 0 Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.263.net (Postfix) with ESMTP id 846344448; Thu, 17 Dec 2015 11:38:17 +0800 (CST) X-RL-SENDER: mark.yao@rock-chips.com X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: mark.yao@rock-chips.com X-UNIQUE-TAG: <0c01eb61483dae282d6463d9d3de70b3> X-ATTACHMENT-NUM: 0 X-SENDER: yzq@rock-chips.com X-DNS-TYPE: 0 Received: from unknown (unknown [58.22.7.114]) by smtp.263.net (Postfix) whith SMTP id 6502B9A1P0; Thu, 17 Dec 2015 11:38:19 +0800 (CST) From: Mark Yao To: David Airlie , Heiko Stuebner , dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/6] drm/rockchip: vop: spilt scale regsters Date: Thu, 17 Dec 2015 11:37:04 +0800 Message-Id: <1450323426-32109-5-git-send-email-mark.yao@rock-chips.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1450323426-32109-1-git-send-email-mark.yao@rock-chips.com> References: <1450323426-32109-1-git-send-email-mark.yao@rock-chips.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151216_193843_826387_23C6AAAD X-CRM114-Status: GOOD ( 10.11 ) X-Spam-Score: -1.9 (-) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Yao MIME-Version: 1.0 Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP There are two version scale control register found on vop, scale full version found on rk3288, support extension registers. and scale little version found on rk3036, only support common scale. Signed-off-by: Mark Yao --- drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 46 ++++++++++++++++++--------- drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 14 ++++++-- drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 5 ++- 3 files changed, 47 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c index bbb781c..d83bf87 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c @@ -50,6 +50,8 @@ REG_SET(x, win->base, win->phy->name, v, RELAXED) #define VOP_SCL_SET(x, win, name, v) \ REG_SET(x, win->base, win->phy->scl->name, v, RELAXED) +#define VOP_SCL_SET_EXT(x, win, name, v) \ + REG_SET(x, win->base, win->phy->scl->ext->name, v, RELAXED) #define VOP_CTRL_SET(x, name, v) \ REG_SET(x, 0, (x)->data->ctrl->name, v, NORMAL) @@ -313,6 +315,20 @@ static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win, return; } + if (!win->phy->scl->ext) { + VOP_SCL_SET(vop, win, scale_yrgb_x, + scl_cal_scale2(src_w, dst_w)); + VOP_SCL_SET(vop, win, scale_yrgb_y, + scl_cal_scale2(src_h, dst_h)); + if (is_yuv) { + VOP_SCL_SET(vop, win, scale_cbcr_x, + scl_cal_scale2(src_w, dst_w)); + VOP_SCL_SET(vop, win, scale_cbcr_y, + scl_cal_scale2(src_h, dst_h)); + } + return; + } + yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w); yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h); @@ -330,7 +346,7 @@ static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win, lb_mode = scl_vop_cal_lb_mode(src_w, false); } - VOP_SCL_SET(vop, win, lb_mode, lb_mode); + VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode); if (lb_mode == LB_RGB_3840X2) { if (yrgb_ver_scl_mode != SCALE_NONE) { DRM_ERROR("ERROR : not allow yrgb ver scale\n"); @@ -354,14 +370,14 @@ static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win, false, vsu_mode, &vskiplines); VOP_SCL_SET(vop, win, scale_yrgb_y, val); - VOP_SCL_SET(vop, win, vsd_yrgb_gt4, vskiplines == 4); - VOP_SCL_SET(vop, win, vsd_yrgb_gt2, vskiplines == 2); + VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4); + VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2); - VOP_SCL_SET(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode); - VOP_SCL_SET(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode); - VOP_SCL_SET(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL); - VOP_SCL_SET(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL); - VOP_SCL_SET(vop, win, yrgb_vsu_mode, vsu_mode); + VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode); + VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode); + VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL); + VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL); + VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode); if (is_yuv) { val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w, dst_w, true, 0, NULL); @@ -370,13 +386,13 @@ static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win, dst_h, false, vsu_mode, &vskiplines); VOP_SCL_SET(vop, win, scale_cbcr_y, val); - VOP_SCL_SET(vop, win, vsd_cbcr_gt4, vskiplines == 4); - VOP_SCL_SET(vop, win, vsd_cbcr_gt2, vskiplines == 2); - VOP_SCL_SET(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode); - VOP_SCL_SET(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode); - VOP_SCL_SET(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL); - VOP_SCL_SET(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL); - VOP_SCL_SET(vop, win, cbcr_vsu_mode, vsu_mode); + VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4); + VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2); + VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode); + VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode); + VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL); + VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL); + VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode); } } diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h index cbb114a..9a44153 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h @@ -66,7 +66,8 @@ struct vop_intr { struct vop_reg clear; struct vop_reg status; }; -struct vop_scl_regs { + +struct vop_scl_extension { struct vop_reg cbcr_vsd_mode; struct vop_reg cbcr_vsu_mode; struct vop_reg cbcr_hsd_mode; @@ -87,8 +88,12 @@ struct vop_scl_regs { struct vop_reg bic_coe_sel; struct vop_reg cbcr_axi_gather_en; struct vop_reg yrgb_axi_gather_en; - struct vop_reg lb_mode; +}; + +struct vop_scl_regs { + const struct vop_scl_extension *ext; + struct vop_reg scale_yrgb_x; struct vop_reg scale_yrgb_y; struct vop_reg scale_cbcr_x; @@ -242,6 +247,11 @@ static inline uint16_t scl_cal_scale(int src, int dst, int shift) return ((src * 2 - 3) << (shift - 1)) / (dst - 1); } +static inline uint16_t scl_cal_scale2(int src, int dst) +{ + return (src - 1) << 12 / (dst - 1); +} + #define GET_SCL_FT_BILI_DN(src, dst) scl_cal_scale(src, dst, 12) #define GET_SCL_FT_BILI_UP(src, dst) scl_cal_scale(src, dst, 16) #define GET_SCL_FT_BIC(src, dst) scl_cal_scale(src, dst, 16) diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c index d47bfc3..6495114 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c @@ -50,7 +50,7 @@ static const uint32_t formats_234[] = { DRM_FORMAT_BGR565, }; -static const struct vop_scl_regs win_full_scl = { +static const struct vop_scl_extension win_full_ext = { .cbcr_vsd_mode = VOP_REG(WIN0_CTRL1, 0x1, 31), .cbcr_vsu_mode = VOP_REG(WIN0_CTRL1, 0x1, 30), .cbcr_hsd_mode = VOP_REG(WIN0_CTRL1, 0x3, 28), @@ -72,6 +72,9 @@ static const struct vop_scl_regs win_full_scl = { .cbcr_axi_gather_en = VOP_REG(WIN0_CTRL1, 0x1, 1), .yrgb_axi_gather_en = VOP_REG(WIN0_CTRL1, 0x1, 0), .lb_mode = VOP_REG(WIN0_CTRL0, 0x7, 5), +}; + +static const struct vop_scl_regs win_full_scl = { .scale_yrgb_x = VOP_REG(WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), .scale_yrgb_y = VOP_REG(WIN0_SCL_FACTOR_YRGB, 0xffff, 16), .scale_cbcr_x = VOP_REG(WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),