| Message ID | 1453326560-20475-1-git-send-email-heiko@sntech.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 01/20/2016 01:49 PM, Heiko Stuebner wrote: > Both clusters have their mux bit in bit 7 of their respective register. > For whatever reason the big cluster currently lists bit 15 which is > definitly wrong. > > Fixes: 3536c97a52db ("clk: rockchip: add rk3368 clock controller") > Reported-by: Zhang Qing <zhangqing@rock-chips.com> > Signed-off-by: Heiko Stuebner <heiko@sntech.de> > --- > I plan to include them into my clk-fixes branch, so posted for reference > and possible objections ;-) None of these patches are fixes to regressions introduced in the merge window for v4.5, so we wouldn't be considering them for clk-fixes. We can certainly queue them up in clk-next for v4.6 and let stable process funnel them to the right stable trees though.
Am Mittwoch, 20. Januar 2016, 14:06:27 schrieb Stephen Boyd: > On 01/20/2016 01:49 PM, Heiko Stuebner wrote: > > Both clusters have their mux bit in bit 7 of their respective register. > > For whatever reason the big cluster currently lists bit 15 which is > > definitly wrong. > > > > Fixes: 3536c97a52db ("clk: rockchip: add rk3368 clock controller") > > Reported-by: Zhang Qing <zhangqing@rock-chips.com> > > Signed-off-by: Heiko Stuebner <heiko@sntech.de> > > --- > > I plan to include them into my clk-fixes branch, so posted for reference > > and possible objections ;-) > > None of these patches are fixes to regressions introduced in the merge > window for v4.5, so we wouldn't be considering them for clk-fixes. We > can certainly queue them up in clk-next for v4.6 and let stable process > funnel them to the right stable trees though. ok, I'll move them over to that part then :-)
hi: On 01/20/2016 01:49 PM, Heiko Stuebner wrote: > Both clusters have their mux bit in bit 7 of their respective register. > For whatever reason the big cluster currently lists bit 15 which is > definitly wrong. > > Fixes: 3536c97a52db ("clk: rockchip: add rk3368 clock controller") > Reported-by: Zhang Qing <zhangqing@rock-chips.com> > Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: zhangqing <zhangqing@rock-chips.com> > --- > I plan to include them into my clk-fixes branch, so posted for reference > and possible objections ;-) > > drivers/clk/rockchip/clk-rk3368.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/clk/rockchip/clk-rk3368.c b/drivers/clk/rockchip/clk-rk3368.c > index 21f3ea9..f6667b8 100644 > --- a/drivers/clk/rockchip/clk-rk3368.c > +++ b/drivers/clk/rockchip/clk-rk3368.c > @@ -165,7 +165,7 @@ static const struct rockchip_cpuclk_reg_data rk3368_cpuclkb_data = { > .core_reg = RK3368_CLKSEL_CON(0), > .div_core_shift = 0, > .div_core_mask = 0x1f, > - .mux_core_shift = 15, > + .mux_core_shift = 7, > }; > > static const struct rockchip_cpuclk_reg_data rk3368_cpuclkl_data = { >
diff --git a/drivers/clk/rockchip/clk-rk3368.c b/drivers/clk/rockchip/clk-rk3368.c index 21f3ea9..f6667b8 100644 --- a/drivers/clk/rockchip/clk-rk3368.c +++ b/drivers/clk/rockchip/clk-rk3368.c @@ -165,7 +165,7 @@ static const struct rockchip_cpuclk_reg_data rk3368_cpuclkb_data = { .core_reg = RK3368_CLKSEL_CON(0), .div_core_shift = 0, .div_core_mask = 0x1f, - .mux_core_shift = 15, + .mux_core_shift = 7, }; static const struct rockchip_cpuclk_reg_data rk3368_cpuclkl_data = {
Both clusters have their mux bit in bit 7 of their respective register. For whatever reason the big cluster currently lists bit 15 which is definitly wrong. Fixes: 3536c97a52db ("clk: rockchip: add rk3368 clock controller") Reported-by: Zhang Qing <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> --- I plan to include them into my clk-fixes branch, so posted for reference and possible objections ;-) drivers/clk/rockchip/clk-rk3368.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)