From patchwork Fri Sep 2 00:54:38 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Lin X-Patchwork-Id: 9310223 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 7D243607D6 for ; Fri, 2 Sep 2016 01:00:52 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7228F295FB for ; Fri, 2 Sep 2016 01:00:52 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 66809295F8; Fri, 2 Sep 2016 01:00:52 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 27497295F8 for ; Fri, 2 Sep 2016 01:00:52 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1bfcqh-00043B-Cp; Fri, 02 Sep 2016 01:00:51 +0000 Received: from lucky1.263xmail.com ([211.157.147.133]) by bombadil.infradead.org with esmtps (Exim 4.85_2 #1 (Red Hat Linux)) id 1bfcqe-000413-Tb for linux-rockchip@lists.infradead.org; Fri, 02 Sep 2016 01:00:50 +0000 Received: from shawn.lin?rock-chips.com (unknown [192.168.167.232]) by lucky1.263xmail.com (Postfix) with ESMTP id BBC2154071; Fri, 2 Sep 2016 09:00:25 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 1 X-MAIL-DELIVERY: 0 X-KSVirus-check: 0 X-ABS-CHECKED: 4 X-ADDR-CHECKED: 0 Received: from localhost.localdomain (localhost [127.0.0.1]) by smtp.263.net (Postfix) with ESMTP id 3CB4D378; Fri, 2 Sep 2016 09:00:20 +0800 (CST) X-RL-SENDER: shawn.lin@rock-chips.com X-FST-TO: heiko@sntech.de X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: shawn.lin@rock-chips.com X-UNIQUE-TAG: <01886b73d6fc7a0db45ced0886decc42> X-ATTACHMENT-NUM: 0 X-SENDER: lintao@rock-chips.com X-DNS-TYPE: 0 Received: from unknown (unknown [58.22.7.114]) by smtp.263.net (Postfix) whith SMTP id 18869KOXL9I; Fri, 02 Sep 2016 09:00:25 +0800 (CST) From: Shawn Lin To: Heiko Stuebner , Rob Herring , Ulf Hansson Subject: [PATCH v3 1/4] Documentation: mmc: sdhci-of-arasan: Add clk_syscon as an optional one Date: Fri, 2 Sep 2016 08:54:38 +0800 Message-Id: <1472777681-16656-2-git-send-email-shawn.lin@rock-chips.com> X-Mailer: git-send-email 1.8.0 In-Reply-To: <1472777681-16656-1-git-send-email-shawn.lin@rock-chips.com> References: <1472777681-16656-1-git-send-email-shawn.lin@rock-chips.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160901_180049_337264_69B559A6 X-CRM114-Status: UNSURE ( 8.49 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Shawn Lin , Ziyuan Xu , linux-mmc@vger.kernel.org, Douglas Anderson , Adrian Hunter , linux-rockchip@lists.infradead.org MIME-Version: 1.0 Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP We introduced soc-ctl-syscon to do several things, for instance, update baseclk or update clkmul, etc. In odrder to access this physical block, we need to explicitly enable its clock. Currently we don't control this clock as we always add a CLK_IGNORE_UNUSED flag for it to indicate that we will not gate it even if not referenced. This is not a correct way since it is a clock parenting from clk_ahb which is used by sdhci-of-arasan now. Without enabling clk_ahb, the flag don't guarantee we could access soc-ctl-syscon. Moreover, we can't find a reason not to gate clk_syscon once we remove/power-down emmc controller. So let's add clk_syscon and enable/disable it explicitly when needed. Signed-off-by: Shawn Lin --- Changes in v3: None Changes in v2: None Documentation/devicetree/bindings/mmc/arasan,sdhci.txt | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt index 3404afa..b04eb02 100644 --- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt +++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt @@ -33,6 +33,9 @@ Optional Properties: - clock-output-names: If specified, this will be the name of the card clock which will be exposed by this device. Required if #clock-cells is specified. + - clock-names: From clock bindings: Although we treat clock-names as required + property, there is still one, "clk_syscon", should be optional as it depends + on whether we need to control soc-ctl-syscon or not. - #clock-cells: If specified this should be the value <0>. With this property in place we will export a clock representing the Card Clock. This clock is expected to be consumed by our PHY. You must also specify @@ -62,8 +65,8 @@ Example: compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; reg = <0x0 0xfe330000 0x0 0x10000>; interrupts = ; - clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>; - clock-names = "clk_xin", "clk_ahb"; + clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>, <&cru ACLK_EMMC_GRF>; + clock-names = "clk_xin", "clk_ahb", "clk_syscon"; arasan,soc-ctl-syscon = <&grf>; assigned-clocks = <&cru SCLK_EMMC>; assigned-clock-rates = <200000000>;