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[1/4] Documentation: bindings: add uphy-dp-sel for Rockchip USB Type-C PHY

Message ID 1486712654-15431-2-git-send-email-zyw@rock-chips.com
State New, archived
Headers show

Commit Message

Chris Zhong Feb. 10, 2017, 7:44 a.m. UTC
rockchip,uphy-dp-sel is the register of type-c phy enable DP function.

Signed-off-by: Chris Zhong <zyw@rock-chips.com>
---

 Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt | 5 +++++
 1 file changed, 5 insertions(+)

Comments

Rob Herring Feb. 16, 2017, 2:20 a.m. UTC | #1
On Fri, Feb 10, 2017 at 03:44:11PM +0800, Chris Zhong wrote:
> rockchip,uphy-dp-sel is the register of type-c phy enable DP function.

"dt-bindings: phy:" is the preferred subject prefix.

> 
> Signed-off-by: Chris Zhong <zyw@rock-chips.com>
> ---
> 
>  Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt | 5 +++++
>  1 file changed, 5 insertions(+)

Otherwise,

Acked-by: Rob Herring <robh@kernel.org>
Chris Zhong Feb. 16, 2017, 3:14 a.m. UTC | #2
Hi Rob

On 02/16/2017 10:20 AM, Rob Herring wrote:
> On Fri, Feb 10, 2017 at 03:44:11PM +0800, Chris Zhong wrote:
>> rockchip,uphy-dp-sel is the register of type-c phy enable DP function.
> "dt-bindings: phy:" is the preferred subject prefix.
OK, I will change the header next version.
dt-bindings: phy: add uphy-dp-sel for Rockchip USB Type-C PHY.

>
>> Signed-off-by: Chris Zhong <zyw@rock-chips.com>
>> ---
>>
>>   Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt | 5 +++++
>>   1 file changed, 5 insertions(+)
> Otherwise,
>
> Acked-by: Rob Herring <robh@kernel.org>
>
>
>
diff mbox

Patch

diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt b/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt
index 6ea867e..c3be83b 100644
--- a/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt
+++ b/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt
@@ -33,6 +33,9 @@  offset, enable bit, write mask bit.
  - rockchip,pipe-status : the register of type-c phy pipe status.
    for type-c phy0, it must be <0xe5c0 0 0>;
    for type-c phy1, it must be <0xe5c0 16 16>;
+ - rockchip,uphy-dp-sel : the register of type-c phy enable DP function
+   for type-c phy0, it must be <0x6268 19 19>;
+   for type-c phy1, it must be <0x6268 3 19>;
 
 Required nodes : a sub-node is required for each port the phy provides.
 		 The sub-node name is used to identify dp or usb3 port,
@@ -62,6 +65,7 @@  Example:
 		rockchip,usb3tousb2-en = <0xe580 3 19>;
 		rockchip,external-psm = <0xe588 14 30>;
 		rockchip,pipe-status = <0xe5c0 0 0>;
+		rockchip,uphy-dp-sel = <0x6268 19 19>;
 
 		tcphy0_dp: dp-port {
 			#phy-cells = <0>;
@@ -90,6 +94,7 @@  Example:
 		rockchip,usb3tousb2-en = <0xe58c 3 19>;
 		rockchip,external-psm = <0xe594 14 30>;
 		rockchip,pipe-status = <0xe5c0 16 16>;
+		rockchip,uphy-dp-sel = <0x6268 3 19>;
 
 		tcphy1_dp: dp-port {
 			#phy-cells = <0>;