From patchwork Wed Aug 23 07:02:19 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Lin X-Patchwork-Id: 9916745 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id B7EF2603FF for ; Wed, 23 Aug 2017 07:04:01 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A98B62893D for ; Wed, 23 Aug 2017 07:04:01 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9DB712896B; Wed, 23 Aug 2017 07:04:01 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Flag: YES X-Spam-Level: ** X-Spam-Status: Yes, score=2.6 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, RCVD_IN_BL_SPAMCOP_NET, RCVD_IN_DNSWL_LOW, RCVD_IN_SBL_CSS, RCVD_IN_SORBS_SPAM autolearn=no version=3.3.1 X-Spam-Report: * -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low * trust * [65.50.211.133 listed in list.dnswl.org] * 1.3 RCVD_IN_BL_SPAMCOP_NET RBL: Received via a relay in bl.spamcop.net * [Blocked - see ] * 3.3 RCVD_IN_SBL_CSS RBL: Received via a relay in Spamhaus SBL-CSS * [58.22.7.114 listed in zen.spamhaus.org] * 0.5 RCVD_IN_SORBS_SPAM RBL: SORBS: sender is a spam source * [58.22.7.114 listed in dnsbl.sorbs.net] * -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% * [score: 0.0000] * 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily * valid * -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 4C5552893F for ; Wed, 23 Aug 2017 07:04:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=uqjo3xCxwezkXMIsAP1+NJeS6PEzt8JZWSdOKXY5YMA=; b=o2iQ0ON5a1sXftFB9ldsirRTN3 QZ52zehGK1PjmG/Zt0hcBdcgmmplaFvaD0C8AJ8XfTc3SoAHbcvAedeALNNCLIeP+HJ+DAaap1PSm ttloyRU5I74noWQNBEqGYAbAVThIbG5oMkFdwXtEsdWfKVKA2ChxhbtYBSrehUEnltkw/ZT9ZyQW3 abL0QF/9ttYvzVXUzxtmgepOeeL5wWM7lYAgndN8nlBfZQO9MGAOSG1rzVfS1D7L5UwCOrsmX7qr3 WsJ16kCMqDT87/vDBI47JT9GUChU0bUqqwrgXM+Upa5ORBM1tSXKJuXj1d3qUxaRcso9sNDpAVoAg EAwAgx8g==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1dkPho-0007tY-D7; Wed, 23 Aug 2017 07:04:00 +0000 Received: from lucky1.263xmail.com ([211.157.147.134]) by bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1dkPhZ-0007Hg-ER for linux-rockchip@lists.infradead.org; Wed, 23 Aug 2017 07:03:52 +0000 Received: from shawn.lin?rock-chips.com (unknown [192.168.167.158]) by lucky1.263xmail.com (Postfix) with ESMTP id 0E8061169; Wed, 23 Aug 2017 15:03:20 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 1 X-MAIL-DELIVERY: 0 X-KSVirus-check: 0 X-ABS-CHECKED: 4 Received: from localhost.localdomain (localhost [127.0.0.1]) by smtp.263.net (Postfix) with ESMTPA id 466BE3CA; Wed, 23 Aug 2017 15:03:18 +0800 (CST) X-RL-SENDER: shawn.lin@rock-chips.com X-FST-TO: bhelgaas@google.com X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: shawn.lin@rock-chips.com X-UNIQUE-TAG: <6080f843bb87daff0e6c6fb865ee9931> X-ATTACHMENT-NUM: 0 X-SENDER: lintao@rock-chips.com X-DNS-TYPE: 0 Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.263.net (Postfix) whith ESMTP id 7467H78A0B; Wed, 23 Aug 2017 15:03:19 +0800 (CST) From: Shawn Lin To: Bjorn Helgaas Subject: [PATCH v5 02/10] PCI: rockchip: spilt out rockchip_pcie_enable_clocks Date: Wed, 23 Aug 2017 15:02:19 +0800 Message-Id: <1503471739-73811-1-git-send-email-shawn.lin@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1503471673-69478-1-git-send-email-shawn.lin@rock-chips.com> References: <1503471673-69478-1-git-send-email-shawn.lin@rock-chips.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170823_000346_786144_3F75B8A0 X-CRM114-Status: UNSURE ( 7.99 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-pci@vger.kernel.org, Jeffy Chen , Brian Norris , Shawn Lin , linux-rockchip@lists.infradead.org MIME-Version: 1.0 Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Spilt out rockchip_pcie_enable_clocks so that it could be reused by rockchip_pcie_resume_noirq and rockchip_pcie_probe. No functional change intended. Signed-off-by: Shawn Lin --- Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None drivers/pci/host/pcie-rockchip.c | 91 ++++++++++++++++++++-------------------- 1 file changed, 46 insertions(+), 45 deletions(-) diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c index 6dc3d83..52974cf 100644 --- a/drivers/pci/host/pcie-rockchip.c +++ b/drivers/pci/host/pcie-rockchip.c @@ -1373,6 +1373,47 @@ static int rockchip_pcie_wait_l2(struct rockchip_pcie *rockchip) return 0; } +static int rockchip_pcie_enable_clocks( + struct rockchip_pcie *rockchip) +{ + struct device *dev = rockchip->dev; + int err; + + err = clk_prepare_enable(rockchip->aclk_pcie); + if (err) { + dev_err(dev, "unable to enable aclk_pcie clock\n"); + return err; + } + + err = clk_prepare_enable(rockchip->aclk_perf_pcie); + if (err) { + dev_err(dev, "unable to enable aclk_perf_pcie clock\n"); + goto err_aclk_perf_pcie; + } + + err = clk_prepare_enable(rockchip->hclk_pcie); + if (err) { + dev_err(dev, "unable to enable hclk_pcie clock\n"); + goto err_hclk_pcie; + } + + err = clk_prepare_enable(rockchip->clk_pcie_pm); + if (err) { + dev_err(dev, "unable to enable clk_pcie_pm clock\n"); + goto err_clk_pcie_pm; + } + + return 0; + +err_clk_pcie_pm: + clk_disable_unprepare(rockchip->hclk_pcie); +err_hclk_pcie: + clk_disable_unprepare(rockchip->aclk_perf_pcie); +err_aclk_perf_pcie: + clk_disable_unprepare(rockchip->aclk_pcie); + return err; +} + static int __maybe_unused rockchip_pcie_suspend_noirq(struct device *dev) { struct rockchip_pcie *rockchip = dev_get_drvdata(dev); @@ -1420,21 +1461,9 @@ static int __maybe_unused rockchip_pcie_resume_noirq(struct device *dev) } } - err = clk_prepare_enable(rockchip->clk_pcie_pm); - if (err) - goto err_pcie_pm; - - err = clk_prepare_enable(rockchip->hclk_pcie); - if (err) - goto err_hclk_pcie; - - err = clk_prepare_enable(rockchip->aclk_perf_pcie); - if (err) - goto err_aclk_perf_pcie; - - err = clk_prepare_enable(rockchip->aclk_pcie); + err = rockchip_pcie_enable_clocks(rockchip); if (err) - goto err_aclk_pcie; + return err; err = rockchip_pcie_init_port(rockchip); if (err) @@ -1452,13 +1481,9 @@ static int __maybe_unused rockchip_pcie_resume_noirq(struct device *dev) err_pcie_resume: clk_disable_unprepare(rockchip->aclk_pcie); -err_aclk_pcie: clk_disable_unprepare(rockchip->aclk_perf_pcie); -err_aclk_perf_pcie: clk_disable_unprepare(rockchip->hclk_pcie); -err_hclk_pcie: clk_disable_unprepare(rockchip->clk_pcie_pm); -err_pcie_pm: return err; } @@ -1492,29 +1517,9 @@ static int rockchip_pcie_probe(struct platform_device *pdev) if (err) return err; - err = clk_prepare_enable(rockchip->aclk_pcie); - if (err) { - dev_err(dev, "unable to enable aclk_pcie clock\n"); - goto err_aclk_pcie; - } - - err = clk_prepare_enable(rockchip->aclk_perf_pcie); - if (err) { - dev_err(dev, "unable to enable aclk_perf_pcie clock\n"); - goto err_aclk_perf_pcie; - } - - err = clk_prepare_enable(rockchip->hclk_pcie); - if (err) { - dev_err(dev, "unable to enable hclk_pcie clock\n"); - goto err_hclk_pcie; - } - - err = clk_prepare_enable(rockchip->clk_pcie_pm); - if (err) { - dev_err(dev, "unable to enable hclk_pcie clock\n"); - goto err_pcie_pm; - } + err = rockchip_pcie_enable_clocks(rockchip); + if (err) + return err; err = rockchip_pcie_set_vpcie(rockchip); if (err) { @@ -1618,13 +1623,9 @@ static int rockchip_pcie_probe(struct platform_device *pdev) regulator_disable(rockchip->vpcie0v9); err_set_vpcie: clk_disable_unprepare(rockchip->clk_pcie_pm); -err_pcie_pm: clk_disable_unprepare(rockchip->hclk_pcie); -err_hclk_pcie: clk_disable_unprepare(rockchip->aclk_perf_pcie); -err_aclk_perf_pcie: clk_disable_unprepare(rockchip->aclk_pcie); -err_aclk_pcie: return err; }