| Message ID | 1505725539-6309-5-git-send-email-nickey.yang@rock-chips.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Hi Nickey, Am Montag, 18. September 2017, 17:05:37 CEST schrieb Nickey Yang: > clk_24m --> Gate11[14] --> clk_mipidphy_ref --> Gate21[0] --> clk_dphy_pll please try to be a bit more verbose in your commit messages :-) . It looks to me, like this patch does not depend on the other ones and I can just pick it directly. Correct? Heiko > Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com> > --- > arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi > b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index d79e9b3..6aa43fd 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi > @@ -1629,7 +1629,7 @@ > compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; > reg = <0x0 0xff960000 0x0 0x8000>; > interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>; > - clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>, > + clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>, > <&cru SCLK_DPHY_TX0_CFG>; > clock-names = "ref", "pclk", "phy_cfg"; > power-domains = <&power RK3399_PD_VIO>;
Am Montag, 18. September 2017, 17:05:37 CEST schrieb Nickey Yang: > clk_24m --> Gate11[14] --> clk_mipidphy_ref --> Gate21[0] --> clk_dphy_pll > > Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com> applied as fix for 4.14 after polishing the commit message a bit Thanks Heiko
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index d79e9b3..6aa43fd 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1629,7 +1629,7 @@ compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; reg = <0x0 0xff960000 0x0 0x8000>; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>, + clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>, <&cru SCLK_DPHY_TX0_CFG>; clock-names = "ref", "pclk", "phy_cfg"; power-domains = <&power RK3399_PD_VIO>;
clk_24m --> Gate11[14] --> clk_mipidphy_ref --> Gate21[0] --> clk_dphy_pll Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com> --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)